This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
I have inherited the code from someone who left the company and I am taking the code.
The code is a SPI driver of the ADS1256 in VHDL that I am adapting now to ADS124S08
So I would to know what is the equivalent of :
t6 : Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands of 50 τCLKIN
in the ADS124S08 ... I have not found an equivalent timing
Thank you
Hi Cyril,
There is no equivalent delay time for the ADS124S08. You can see in Table 7.6 in the ADS124S08 datasheet that the "delay time between bytes or commands" is 0 ns. Moreover, Section 9.5.4.2 shows and states that data on DOUT occurs on the first SCLK rising edge after the command on DIN.
-Bryan