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ADS8528: Design related queries for application development

Manish Sharma2
Intellectual 380 points
Part Number: ADS8528
Other Parts Discussed in Thread: TLV9064, REF50

Hi,

We are using ADS8528 for our development. Regarding the same we have some queries regarding the interface and the functionality.

We are using ADS8528 in our development boards with following configuration,

 

  1. HW Mode
  2. All CONVST_x tied together
  3. External Vref
  4. Internal clock
  5. Data collection through SDO_A and SDI line using in Serial mode (SPI).
  6. Not in daisy chain mode. Separate chip select for each ADC
  7. Over all 3 ADC used

 With respect to the above configuration following are the queries regarding the functionality of ADS8528,

 1. When used in HW mode with all CONVST_x tied together BUSY/INT (bit 27) act in INT mode. In order to configure this  do we need to configure the config register using SPI line in SW mode? Also to change the polarity of the INT (Bit C26)

2. Now as per point 1, we need to change HW/SW pin to Software mode. Now, since the ADC is in SW mode, what is the status of other pins on the ADC like RANGE/XCLK? Since in HW mode, RANGE is configured for 2xVREF = 5V bipolar input, but in SW mode this pin behaves as external XCLK signal. How is RANGE defined in this case during the time the ADC remains in the SW mode? Will it change according to CONFIG register and reinitialize when device goes back to HW mode after config register update is complete?

3.  In page 16 of the datasheet, tXCLK is mentioned as 66.67ns and clock cycles per conversion is 19-20 cycles. So, the conversion time tCONV=1.33us. But in HW mode by default, the device uses the internal clock CCLK for conversion, for which tCCLK is not mentioned in the datasheet. Is it the same as tXCLK?

4.  The absolute maximum analogue input range on ADS8528 are HVSS-0.3V to HVDD+0.3V. In page 9, the HVDD minimum recommended voltage is specified as 5V, but the electrical characteristics are defined at HVDD=15V and HVSS=-15V. Since in our design we are using HVDD=5V, HVSS=0V, what will be the performance degradation when HVDD is at this minimum recommended voltage? Even though TLV9064 rails have been changed to 5V, the ADC input will be restricted to at least 100 ADC count below upper rail. Will there be a performance impact in that case?

Also refer the updated attached schematic of all ADC and the reference (Vref) circuit, w.r.t above mentioned configuration and review the same and revert ASAP.

 Schematic for TI review.pdf

Best Regards,

Manish Sharma

  • 0
    TI__Mastermind 25030 points

    Hello Manish, 

    1. With all CONVST tied together, the BUSY signal may be used as an interrupt, but does not have to. You are able to config 27 = 1 in your case to use as an interrupt, but you can leave it as a busy. But as you noted, to change config bit 27, you will need to do so using software mode. You are able to switch back and forth between software and hardware mode, thus you can change register content using software mode, and then switch back to hardware mode. This applies to CONGIF bit 26, polarity as well.
    2. After the ADC is switched from HW mode to SW mode, the pin 34 (RANGE/XCLK) will act according to CONFIG bit 29 and 28, which are ‘00’ by default. The ‘00’ indicates that the ADC is in a normal operation, the internal conversion clock will not be shown on pin 34 unless the bit 28 is changed from 0 to 1. Therefore, there is no impact for the customer’s high voltage configuration on the pin 34 for selecting 2xVREF = 5V bipolar input range.
    3. Page 17 of the datasheet specifies the internal conversion clock. Note that when CLKSEL=0, this means CCLK is used. this parameter determines the maximum sampling rate on ADS8528 is 1/(1.33us+280ns) = 621ksps. The 650ksps sampling rate specified for ADS8528 in the 1st page can only be achieved when an external clock (tXCLK) is used.
    4. To meet the specifications listed in the ADS8528 datasheet, a minimum 1.5V headroom on both HVDD and HVSS are needed. For 0-5V input signal, the recommended supply conditions should be 6.5 V ≤ HVDD ≤ 16.5 V and -16.5 V ≤ HVSS ≤ -1.5 V.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    TI__Mastermind 25030 points

    Hello Manish,

    I overlooked the schematic, below are my notes on the schematic you provided 

    - at the output of the REF5025, there are 3 capacitors, at the input of the TLV9064 This is too big of a load for the REF to drive. the datasheet for the reference will have details on what size capacitor should be used here. Also, the ADS8528 has internal buffers driving the reference, these are accessible to use with the internal reference or the external reference. 

    Regards

    Cynthia 

  • 0 in reply to Cynthia
    Intellectual 380 points

    Hello Cynthia,

    Thanks for your response. However the schematic we have prepared is based on the datasheet of of ADS8528 page 44 as shown.

    Kindly revert as per the datasheet schematic if any modification is required.

    Few more things are also need to be discussed:

    1. Our application demands the use of this ADC in unipolar mode instead of bipolar. Will it be possible to use it in this fashion.

    2. Will the range remain same for unipolar application ? (as datasheet specified it for bipolar application). With Ref voltage of 2.5V and input voltage range of 0-5V, for 2.5V we are getting 1024 as DC count instead of 2048, so effectively we are utilizing the half of the available headroom. please clarify if anything we understood is incorrect. how to utilize it for the full range how to use it in our application.

    3. Do we have source code of ADC interfacing in serial mode. If yes kindly share.

     

    Request you to please revert ASAP. since we are in a stage of finalizing our design with this part.

    Thanks

    Manish Sharma

  • 0 in reply to Manish Sharma2
    TI__Mastermind 25030 points

    Let me look into this further. 

    1 the device is a bipolar device, the range can only be change to x2Vref or x4Vref, into the negative and positive range, 

    If you will only positive polarity inputs, then you will only be using half the input range. The device input range cannot be made unipolar. 

    3. we doo not have a sample code, unfortunately. I suggest using scope probes on the digital lines to provide a visual check on the communication bus and confirming timing requirement are met. 

  • 0 in reply to Cynthia
    TI__Guru 56345 points

    Hi Manish,

    According to the REF50 datasheet, it is suggested that the output capacitance should be between 1uF and 50uF.  See below:

    Ben

  • 0 in reply to Ben C
    TI__Guru 56345 points

    Hi Manish,

    If there are no further questions, please close the thread by clicking on "resolved".  Thank you and good luck to you!

    Ben