• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 45 subscribers
  • Views 330 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADS8586S: Power consumption calculation

ADS8586S: Maximum sampling rate possible?

Vineeth N
Expert 1180 points
Part Number: ADS8586S
Other Parts Discussed in Thread: ADS8686S

Hi Team,

I doubt the maximum sampling rate possible for ADS8586s. It is given in the datasheet that the maximum sampling rate for this chip is 250 ksps. Now my question is can I sample all the 6 channels at a max sampling rate of 250 ksps simultaneously or the maximum sampling rate possible will be 41.6 ksps (250/6) per channel if I am sampling simultaneously? 

And my understanding is like if I am sampling at 250 ksps for all the 6 channels, then by the end of one conversion cycle all the 6 channel results will be ready. Now all I have to do is to push the data out through SPI. Is this correct? 

Regards,

Vineeth

  • 0
    TI__Mastermind 45725 points

    Hi Vineeth,

    ADS8686S is a simultaneous sampling ADC, 250ksps per channel sampling rate is supported on this ADC. If the Serial interface is used, the conversion data for each channel will be shifted out to SDO line one by one. However, note that the data for each channel was sampled at the same time and this is why it is called simultaneous sampling. I hope this helps.

    Best regards,

    Dale

  • 0 in reply to Dale Li
    Expert 1180 points

    Hi Dale,

    Thank you for your response. So if I am sampling at 250ksps I will get samples at every 4us. Then to transmit the results of 6 channels, I will get data transmission time around 4us. So 4us for a total of 16*6-bit data will give SCLK value 4/96= 41.6ns (other time parameters are not considered), which I guess is below the minimum clock frequency tclk (50ns) required by the IC. This got me confused.

    Regards,

    Vineeth 

  • +1 in reply to Vineeth N
    TI__Mastermind 45725 points

    Hi Vineeth,

    Understood. The data transmission for all 6 channels needs total 16x6=96 SCLK clocks in serial interface, so when only one DOUT is selected and the SCLK is 20MHz according to the data sheet, the total cycle time:

    tcycle = 64xtSCLK+ tCONV =96x50ns+3us ≈ 8us, so the maximum sampling rate per channel is 125ksps.

    With a similar calculation, the maximum sampling rate per channel is 250ksps when both DOUTA and DOUTB are selected.

    However, the ADS8586Sdevice actually supports 50MHz maximum SCLK frequency, so 250ksps sampling rate is actually supported with only one DOUT line. The data sheet should be updated in next revision.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Expert 1180 points

    Hi Dale,

    Thank you for your response and detailed explanation. I understand it now.

    Regards,

    Vineeth