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Dear Team,
A related question to: e2e.ti.com/.../ads1251-sigma-delta-switching-frequency-synchronization
"Since I am using 100% of FPGA pins, I am summing clock,serial clock, the same for all chips. And just MISO pins will be different for each channel. If I use the same timing on all channels, does that mean it will be synchronized all the time ?
I can pull back timing if needed, all I care is to get 1kHz sampling rate ( or oversample in hardware as much as possible to get even more better noise floor)"
Can you offer any advice?
Thank you,
Daniel
Hi Daniel,
There is a way to synchronize multiple ADS1251s, which is described on page 11 in the ADC datasheet.
The only consideration would be the actual trace length, etc., on the PCB that could cause minor differences between when the clock pulses are sent and when they are received by each ADC. But this would probably be imperceptible compared to the actual data rate.
-Bryan