Hello,
I have the exact same setup as the OP (Connie,) and I don't feel that the answer given was sufficient. There are 96 clock cycles in the SPI transaction - only 32 of which are needed for the SDI to each chip. She asked "Where does the 32 bits for the control register fit into the 96 clock transfer?". Figure 2 on page 15 of the datasheet only shows a 32-bit transaction.
Currently, I am just repeating the 32-bit Control Register value 3x for the 96-bit transaction, but that doesn't appear to work. I need to do a RESET between conversion attempts in order to get it to work, which is obviously less than ideal.
Any thoughts?
Thanks.
-Bob