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ADS4225EVM: Questions about timing constraints, clocks and input delay primitives

Part Number: ADS4225EVM
Other Parts Discussed in Thread: TSW1418EVM, TSW14DL3200EVM

Hi
I have read instructions in SLAA545(Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)) about interfacing ADS42XX boards to FPGA developments boards. I have read the Datasheet and I placed the constraints needes. However I'm not getting good timing (it's functional at least). I'm sampling at approximately 80MSPS so: 


create_clock -period 10.000 -name aclk -waveform {0.000 5.000} [get_ports -filter { NAME =~  "*aclk*" && DIRECTION == "IN" }]
create_clock -period 13.468 -name ADC_CLK [get_ports {FMC_LA[17]}]
create_clock -period 13.468 -name ADC_CLK_LAUNCH -waveform {3.367 16.835}
create_generated_clock -name ADC_GEN_CLOCK -source [get_pins PLLE2_BASE_inst/CLKIN1] -multiply_by 1 [get_pins PLLE2_BASE_inst/CLKOUT0]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]

However i'm getting hold slack issues. I placed IODELAY blocks, but hold slack is intact. How I can time the ninterface properly?

  • Alejandro,

    What family of FPGA are you interfacing to? Are you using a PLL? Please provide more info regarding your firmware and/or send the interface source code if possible.

    Regards,

    Jim

  • I'm using a Xilinx Artix 7 Xc7a200t in a nexys video board. I'm using vivado2021.2 . This is the current source code (less non relevant parts)

    RTL

    -------------------------------------------------------------------------------
    -- Title      : ios
    -- Project    : 
    -------------------------------------------------------------------------------
    -- File       : io_1.vhd
    -- Author     : Alejandro Estay  <aestay@dts.cl>
    -- Company    : DTS SpA.
    -- Created    : 2021-12-02
    -- Last update: 2021-12-09
    -- Platform   : Vivado, artix-7
    -- Standard   : VHDL'08
    -------------------------------------------------------------------------------
    -- Description: sistema basico de entrada de adc TI ADS42XX
    -------------------------------------------------------------------------------
    -- Copyright (c) 2021 DTS SpA.
    -------------------------------------------------------------------------------
    -- Revisions  :
    -- Date        Version  Author  Description
    -- 2021-12-02  1.0      aestay  Created
    -------------------------------------------------------------------------------
    
    
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.numeric_std.all;
    
    library UNISIM;
    use UNISIM.VComponents.all;
    
    library xpm;
    use xpm.vcomponents.all;
    
    entity ios is
    	generic(of_buttons        : integer := 13;
    	        of_buttons_input  : integer := 2;
    	        of_buttons_output : integer := 8);
    	port (
    		led              : out std_logic_vector(7 downto 0);
    		sw               : in  std_logic_vector(of_buttons -1 downto 0);
    		set_vadj         : out std_logic_vector(1 downto 0);
    		vadj_en          : out std_logic;
    		aclk             : in  std_logic;
    		cpu_resetn       : in  std_logic;
    		FMC_LA, FMC_LA_N : in  std_logic_vector(33 downto 0);
    		jb               : in  std_logic_vector(7 downto 0)
    	);
    end ios;
    
    architecture Behavioral of ios is
    
    	signal FMC_LA_BUS                                      : std_logic_vector(33 downto 0);
    	signal ADC_DA_BUS,ADC_DA_BUS_ND, ADC_DB_BUS, ADC_DC_BUS, ADC_DD_BUS                 : std_logic_vector(0 to 5);
    	signal ADC_DA_BUS_SDR, ADC_DB_BUS_SDR, ADC_DC_BUS_SDR, ADC_DD_BUS_SDR : std_logic_vector(0 to 11);
    
    	signal ADC_CLK_IBUFDS_O                                     : std_logic;
    	signal sys_reset_0, inp_reset_1, sys_resetn_0, inp_resetn_1 : std_logic_vector(0 downto 0);
    	signal sys_reset, inp_reset, sys_resetn, inp_resetn         : std_logic;
    	signal read_clock                                           : std_logic;
    	signal write_clock                                          : std_logic;
    	signal dcm_locked_1, dcm_locked_2                           : std_logic;
    	signal clock_fb, clock_fb_sys                               : std_logic;
    	signal up_down                                              : std_logic_vector(1 downto 0);
    	type pss_state_type is (init, mmcm_wait, mmcm_ready, button_press, button_wait);
    
    	signal pss_state, pss_state_next : pss_state_type;
    
    
    	signal reset_count_a, reset_count_a_next, reset_count_b, reset_count_b_next         : unsigned(3 downto 0);
    	signal reset_count_a_o, reset_count_a_o_next, reset_count_b_o, reset_count_b_o_next : unsigned (8 downto 0);
    
    
    	------------------------------------------------------------------------------------------------------------------------------
    	signal ref_clk				:		std_logic;
    
    
    	component proc_sys_reset_0
    		port (
    			slowest_sync_clk     : in  std_logic;
    			ext_reset_in         : in  std_logic;
    			aux_reset_in         : in  std_logic;
    			mb_debug_sys_rst     : in  std_logic;
    			dcm_locked           : in  std_logic;
    			mb_reset             : out std_logic;
    			bus_struct_reset     : out std_logic_vector(0 downto 0);
    			peripheral_reset     : out std_logic_vector(0 downto 0);
    			interconnect_aresetn : out std_logic_vector(0 downto 0);
    			peripheral_aresetn   : out std_logic_vector(0 downto 0)
    		);
    	end component;
    
    	component proc_sys_reset_1
    		port (
    			slowest_sync_clk     : in  std_logic;
    			ext_reset_in         : in  std_logic;
    			aux_reset_in         : in  std_logic;
    			mb_debug_sys_rst     : in  std_logic;
    			dcm_locked           : in  std_logic;
    			mb_reset             : out std_logic;
    			bus_struct_reset     : out std_logic_vector(0 downto 0);
    			peripheral_reset     : out std_logic_vector(0 downto 0);
    			interconnect_aresetn : out std_logic_vector(0 downto 0);
    			peripheral_aresetn   : out std_logic_vector(0 downto 0)
    		);
    	end component;
    
    
    begin
    	----------------------------------------------------Reset Block---------------------------------------------------------
    	sys_reset  <= sys_reset_0(0);
    	inp_reset  <= inp_reset_1(0);
    	sys_resetn <= sys_resetn_0(0);
    	inp_resetn <= inp_resetn_1(0);
    	------------------------------------------------------------------------------------------------------------------------
    	-----------------------------------------------------wirebox------------------------------------------------------------
    	--*****************************************************FMC************************************************************--  
    	set_vadj <= "01";
    	vadj_en  <= '1';
    
    	ADC_CLK_IBUFDS_O <= FMC_LA_BUS(17);
    
    	ADC_DA_BUS_ND <= (FMC_LA_BUS(29) & FMC_LA_BUS(14) & FMC_LA_BUS(25) & FMC_LA_BUS(24) & FMC_LA_BUS(21) & FMC_LA_BUS(22));
    	ADC_DB_BUS <= (FMC_LA_BUS(19) & FMC_LA_BUS(15) & FMC_LA_BUS(16) & FMC_LA_BUS(11) & FMC_LA_BUS(12) & FMC_LA_BUS(7));
    	--ADC_DC_BUS          <= (FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(7));
    	--ADC_DD_BUS          <= (FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(7));
    	--*******************************************************************************************************************--
    *------------------------------------------------------------------*
    	PLLE2_BASE_sys : MMCME2_ADV
    		generic map (
    			BANDWIDTH          => "OPTIMIZED",   -- OPTIMIZED, HIGH, LOW
    			CLKFBOUT_MULT_F    => 10.0,  -- Multiply value for all CLKOUT, (2-64)
    			CLKFBOUT_PHASE     => 0.0,  -- Phase offset in degrees of CLKFB, (-360.000-360.000).
    			CLKIN1_PERIOD      => 10.0,  -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    			-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
    			CLKOUT0_DIVIDE_F   => 10.0,       --(100 Mhz)
    			CLKOUT1_DIVIDE     => 30,         --(4.56Mhz)
    			CLKOUT2_DIVIDE     => 5,
    			CLKOUT3_DIVIDE     => 10,
    			CLKOUT4_DIVIDE     => 10,
    			CLKOUT5_DIVIDE     => 10,
    			-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
    			CLKOUT0_DUTY_CYCLE => 0.5,
    			CLKOUT1_DUTY_CYCLE => 0.5,
    			CLKOUT2_DUTY_CYCLE => 0.5,
    			CLKOUT3_DUTY_CYCLE => 0.5,
    			CLKOUT4_DUTY_CYCLE => 0.5,
    			CLKOUT5_DUTY_CYCLE => 0.5,
    			-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
    			CLKOUT0_PHASE      => 0.0,
    			CLKOUT1_PHASE      => 0.0,
    			CLKOUT2_PHASE      => 0.0,
    			CLKOUT3_PHASE      => 0.0,
    			CLKOUT4_PHASE      => 0.0,
    			CLKOUT5_PHASE      => 0.0,
    			DIVCLK_DIVIDE      => 1,          -- Master division value, (1-56)
    			REF_JITTER1        => 0.0,  -- Reference input jitter in UI, (0.000-0.999).
    			STARTUP_WAIT       => true  -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
    		)
    		port map (
    			-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
    			CLKOUT0  => read_clock,           -- 1-bit output: CLKOUT0
    			CLKOUT1  => sw_clock,             -- 1-bit output: CLKOUT1
    			CLKOUT2  => ref_clk,                 -- 1-bit output: CLKOUT2
    			CLKOUT3  => open,                 -- 1-bit output: CLKOUT3
    			CLKOUT4  => open,                 -- 1-bit output: CLKOUT4
    			CLKOUT5  => open,                 -- 1-bit output: CLKOUT5
    			-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
    			CLKFBOUT => clock_fb_sys,         -- 1-bit output: Feedback clock
    			LOCKED   => dcm_locked_1,         -- 1-bit output: LOCK
    			CLKIN1   => aclk,
    			CLKIN2   => '1',
    			CLKINSEL => '1',
    			-- 1-bit input: Input clock
    			-- Control Ports: 1-bit (each) input: PLL control ports
    			PWRDWN   => '0',                  -- 1-bit input: Power-down
    			RST      => not cpu_resetn,       -- 1-bit input: Reset
    			-------------------------------------------------------------------------------------
    			DADDR    => (others => '0'),
    			DCLK     => '0',
    			DI       => (others => '0'),
    			DEN      => '0',
    			DWE      => '0',
    			-----------------------------------------------------------
    			PSCLK    => '0',                  --1-bit input: Phase shift clock
    			PSEN     => '0',                  --1-bit  input: Phase shift enable
    			PSINCDEC => '0',            --1-bit input:Phase shift increment/decrement
    			-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
    			CLKFBIN  => clock_fb_sys          -- 1-bit input: Feedback clock
    		);
    	PLLE2_BASE_inst : MMCME2_ADV
    		generic map (
    			BANDWIDTH           => "OPTIMIZED",  -- OPTIMIZED, HIGH, LOW
    			CLKFBOUT_MULT_F     => 15.0,  -- Multiply value for all CLKOUT, (2-64)
    			CLKFBOUT_PHASE      => 0.00,  -- Phase offset in degrees of CLKFB, (-360.000-360.000).
    			CLKIN1_PERIOD       => 13.468,  -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    			-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
    			CLKOUT0_DIVIDE_F    => 15.0,
    			CLKOUT1_DIVIDE      => 15,
    			CLKOUT2_DIVIDE      => 15,
    			CLKOUT3_DIVIDE      => 15,
    			CLKOUT4_DIVIDE      => 15,
    			CLKOUT5_DIVIDE      => 15,
    			-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
    			CLKOUT0_DUTY_CYCLE  => 0.5,
    			CLKOUT1_DUTY_CYCLE  => 0.5,
    			CLKOUT2_DUTY_CYCLE  => 0.5,
    			CLKOUT3_DUTY_CYCLE  => 0.5,
    			CLKOUT4_DUTY_CYCLE  => 0.5,
    			CLKOUT5_DUTY_CYCLE  => 0.5,
    			-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
    			CLKOUT0_PHASE       => 0.0,
    			CLKOUT1_PHASE       => 0.0,
    			CLKOUT2_PHASE       => 0.0,
    			CLKOUT3_PHASE       => 0.0,
    			CLKOUT4_PHASE       => 0.0,
    			CLKOUT5_PHASE       => 0.0,
    			DIVCLK_DIVIDE       => 1,         -- Master division value, (1-56)
    			REF_JITTER1         => 0.0,  -- Reference input jitter in UI, (0.000-0.999).
    			CLKOUT0_USE_FINE_PS => true,
    			STARTUP_WAIT        => true  -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
    		)
    		port map (
    			-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
    			CLKOUT0  => write_clock,          -- 1-bit output: CLKOUT0
    			CLKOUT1  => open,                 -- 1-bit output: CLKOUT1
    			CLKOUT2  => open,                 -- 1-bit output: CLKOUT2
    			CLKOUT3  => open,                 -- 1-bit output: CLKOUT3
    			CLKOUT4  => open,                 -- 1-bit output: CLKOUT4
    			CLKOUT5  => open,                 -- 1-bit output: CLKOUT5
    			-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
    			CLKFBOUT => clock_fb,             -- 1-bit output: Feedback clock
    			LOCKED   => dcm_locked_2,         -- 1-bit output: LOCK
    			--      CLKIN1    => ADC_CLK_IBUFDS_O,     -- 1-bit input: Input clock
    			CLKIN1   => ADC_CLK_IBUFDS_O,
    			CLKIN2   => '1',
    			CLKINSEL => '1',
    			-- Control Ports: 1-bit (each) input: PLL control ports
    			PWRDWN   => '0',                  -- 1-bit input: Power-down
    			RST      => not cpu_resetn,       -- 1-bit input: Reset
    			---------------------------------------------------------
    			DADDR    => (others => '0'),
    			DCLK     => '0',
    			DI       => (others => '0'),
    			DEN      => '0',
    			DWE      => '0',
    			-----------------------------------------------------------
    			PSCLK    => write_clock,          --1-bit input: Phase shift clock
    			PSEN     => psen,                 --1-bit  input: Phase shift enable
    			PSINCDEC => psincdec,       --1-bitinput:Phase shift increment/decrement
    			PSDONE   => psdone,
    			-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
    			CLKFBIN  => clock_fb              -- 1-bit input: Feedback clock
    		);
    
    	reset_system : proc_sys_reset_0
    		port map(
    			slowest_sync_clk     => sw_clock,
    			ext_reset_in         => cpu_resetn,
    			aux_reset_in         => '0',
    			mb_debug_sys_rst     => '0',
    			dcm_locked           => dcm_locked_1,
    			mb_reset             => open,
    			bus_struct_reset     => open,
    			peripheral_reset     => sys_reset_0,
    			interconnect_aresetn => open,
    			peripheral_aresetn   => sys_resetn_0
    		);
    	reset_input : proc_sys_reset_1
    		port map(
    			slowest_sync_clk     => write_clock,
    			ext_reset_in         => cpu_resetn,
    			aux_reset_in         => '0',
    			mb_debug_sys_rst     => '0',
    			dcm_locked           => dcm_locked_2,
    			mb_reset             => open,
    			bus_struct_reset     => open,
    			peripheral_reset     => inp_reset_1,
    			interconnect_aresetn => open,
    			peripheral_aresetn   => inp_resetn_1
    		);
    
    	generate_FMC_LA : for index in 0 to 33 generate
    		IBUFDS_A : IBUFDS
    			port map (
    				I  => FMC_LA(index),
    				IB => FMC_LA_N(index),
    				O  => FMC_LA_BUS(index)
    			);
    	end generate generate_FMC_LA;
    
    	generate_DDR_A : for index in 0 to 5 generate
    		IDDR_inst_A : IDDR
    			generic map (
    				DDR_CLK_EDGE => "OPPOSITE_EDGE",  			-- "OPPOSITE_EDGE", "SAME_EDGE" 
    				-- or "SAME_EDGE_PIPELINED" 
    				INIT_Q1      => '0',            			-- Initial value of Q1: '0' or '1'
    				INIT_Q2      => '0',            			-- Initial value of Q2: '0' or '1'
    				SRTYPE       => "SYNC")         			-- Set/Reset type: "SYNC" or "ASYNC" 
    			port map (
    				Q1 => ADC_DA_BUS_SDR(2*index),  			-- 1-bit output for positive edge of clock 
    				Q2 => ADC_DA_BUS_SDR(2*index+1),  			-- 1-bit output for negative edge of clock
    				C  => write_clock,              			-- 1-bit clock input
    				CE => dcm_locked_2,             			-- 1-bit clock enable input
    				D  => ADC_DA_BUS(index),        			-- 1-bit DDR data input
    				R  => inp_reset,                			-- 1-bit reset
    				S  => '0'  );                     			-- 1-bit set
        ADC_DA_INPUT_ctrl: IDELAYCTRL
       port map (
          RDY 		=> 	open,       -- 1-bit output: Ready output
          REFCLK 	=> 	ref_clk, -- 1-bit input: Reference clock input
          RST 		=> 	sys_reset);
       	
     	ADC_DA_INPUT_inst : IDELAYE2
       			generic map (
          			CINVCTRL_SEL 			=> "FALSE",         -- Enable dynamic clock inversion (FALSE, TRUE)
          			DELAY_SRC 				=> "IDATAIN",       -- Delay input (IDATAIN, DATAIN)
          			HIGH_PERFORMANCE_MODE 	=> "TRUE", 		-- Reduced jitter ("TRUE"), Reduced power ("FALSE")
          			IDELAY_TYPE 			=> "FIXED",         -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
          			IDELAY_VALUE 			=> 27,               -- Input delay tap setting (0-31)
          			PIPE_SEL 				=> "FALSE",         -- Select pipelined mode, FALSE, TRUE
          			REFCLK_FREQUENCY 		=> 200.0,        	-- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
          			SIGNAL_PATTERN 			=> "DATA"          	-- DATA, CLOCK input signal
       						)
       			port map (
          			DATAOUT 				=> ADC_DA_BUS(index),          -- 1-bit output: Delayed data output
          			C 						=> write_clock,                -- 1-bit input: Clock input
          			CE 						=> '1',
          			cinvctrl 				=> '0',
          			cntvaluein				=> (others=>'0'),
          			datain 					=> '0',
          			inc						=> '0',
          			ld						=> '0',
          			regrst 					=> '0',
          			ldpipeen 				=> '0',
          			IDATAIN 				=> ADC_DA_BUS_ND(index)  );      -- 1-bit input: Data input from the I/O
    
    end generate generate_DDR_A;
    
    

    Timing

    create_clock -period 10.000 -name aclk -waveform {0.000 5.000} [get_ports -filter { NAME =~  "*aclk*" && DIRECTION == "IN" }]
    create_clock -period 13.468 -name ADC_CLK [get_ports {FMC_LA[17]}]
    create_clock -period 13.468 -name ADC_CLK_LAUNCH -waveform {3.367 16.835}
    # IODELAY GROUPS
    
    
    #attribute IODELAY_GROUP of ADC_DA_INPUT_inst:  label is "ADC_A_INPUT_DLY";
    #attribute IODELAY_GROUP of ADC_DA_INPUT_crtl:  label is "ADC_A_INPUT_DLY";
    
    
    set_property IODELAY_GROUP ADC_A_INPUT_DLY [get_cells -filter  {NAME =~ "*ADC_DA_INPUT_inst*"}]
    set_property IODELAY_GROUP ADC_A_INPUT_DLY [get_cells -filter  {NAME =~ "*ADC_DA_INPUT_ctrl*"}]
    #
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
    
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA_N[14]} {FMC_LA_N[29]} {FMC_LA_N[25]} {FMC_LA_N[24]} {FMC_LA_N[21]} {FMC_LA_N[22]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA_N[14]} {FMC_LA_N[29]} {FMC_LA_N[25]} {FMC_LA_N[24]} {FMC_LA_N[21]} {FMC_LA_N[22]}}]
    
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]
    
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA_N[19]} {FMC_LA_N[15]} {FMC_LA_N[16]} {FMC_LA_N[11]} {FMC_LA_N[12]} {FMC_LA_N[7]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA_N[19]} {FMC_LA_N[15]} {FMC_LA_N[16]} {FMC_LA_N[11]} {FMC_LA_N[12]} {FMC_LA_N[7]}}]
    
    #create_generated_clock -name ADC_GEN_CLOCK -source [get_pins PLLE2_BASE_inst/CLKIN1] -multiply_by 1 -invert -add -master_clock [get_clocks ADC_CLK] [get_pins PLLE2_BASE_inst/CLKOUT0]
    create_generated_clock -name ADC_GEN_CLOCK -source [get_pins PLLE2_BASE_inst/CLKIN1] -multiply_by 1 [get_pins PLLE2_BASE_inst/CLKOUT0]

    I/O Placement

    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[0]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[0]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[1]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[1]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[2]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[2]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[3]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[3]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[4]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[4]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[5]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[5]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[6]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[6]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[7]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[7]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[8]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[8]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[9]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[9]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[10]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[10]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[11]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[11]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[12]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[12]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[13]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[13]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[14]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[14]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[15]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[15]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[16]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[16]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[17]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[17]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[18]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[18]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[19]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[19]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[20]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[20]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[21]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[21]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[22]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[22]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[23]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[23]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[24]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[24]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[25]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[25]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[26]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[26]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[27]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[27]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[28]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[28]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[29]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[29]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[30]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[30]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[31]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[31]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[32]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[32]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[33]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[33]}]
    
    set_property PACKAGE_PIN K18 [get_ports {FMC_LA[0]}]
    set_property PACKAGE_PIN K19 [get_ports {FMC_LA_N[0]}]
    set_property PACKAGE_PIN J20 [get_ports {FMC_LA[1]}]
    set_property PACKAGE_PIN J21 [get_ports {FMC_LA_N[1]}]
    set_property PACKAGE_PIN M18 [get_ports {FMC_LA[2]}]
    set_property PACKAGE_PIN L18 [get_ports {FMC_LA_N[2]}]
    set_property PACKAGE_PIN N18 [get_ports {FMC_LA[3]}]
    set_property PACKAGE_PIN N19 [get_ports {FMC_LA_N[3]}]
    set_property PACKAGE_PIN N20 [get_ports {FMC_LA[4]}]
    set_property PACKAGE_PIN M20 [get_ports {FMC_LA_N[4]}]
    set_property PACKAGE_PIN M21 [get_ports {FMC_LA[5]}]
    set_property PACKAGE_PIN L21 [get_ports {FMC_LA_N[5]}]
    set_property PACKAGE_PIN N22 [get_ports {FMC_LA[6]}]
    set_property PACKAGE_PIN M22 [get_ports {FMC_LA_N[6]}]
    set_property PACKAGE_PIN M13 [get_ports {FMC_LA[7]}]
    set_property PACKAGE_PIN L13 [get_ports {FMC_LA_N[7]}]
    set_property PACKAGE_PIN M15 [get_ports {FMC_LA[8]}]
    set_property PACKAGE_PIN M16 [get_ports {FMC_LA_N[8]}]
    set_property PACKAGE_PIN H20 [get_ports {FMC_LA[9]}]
    set_property PACKAGE_PIN G20 [get_ports {FMC_LA_N[9]}]
    set_property PACKAGE_PIN K21 [get_ports {FMC_LA[10]}]
    set_property PACKAGE_PIN K22 [get_ports {FMC_LA_N[10]}]
    set_property PACKAGE_PIN L14 [get_ports {FMC_LA[11]}]
    set_property PACKAGE_PIN L15 [get_ports {FMC_LA_N[11]}]
    set_property PACKAGE_PIN L19 [get_ports {FMC_LA[12]}]
    set_property PACKAGE_PIN L20 [get_ports {FMC_LA_N[12]}]
    set_property PACKAGE_PIN K17 [get_ports {FMC_LA[13]}]
    set_property PACKAGE_PIN J17 [get_ports {FMC_LA_N[13]}]
    set_property PACKAGE_PIN J22 [get_ports {FMC_LA[14]}]
    set_property PACKAGE_PIN H22 [get_ports {FMC_LA_N[14]}]
    set_property PACKAGE_PIN L16 [get_ports {FMC_LA[15]}]
    set_property PACKAGE_PIN K16 [get_ports {FMC_LA_N[15]}]
    set_property PACKAGE_PIN G17 [get_ports {FMC_LA[16]}]
    set_property PACKAGE_PIN G18 [get_ports {FMC_LA_N[16]}]
    set_property PACKAGE_PIN B17 [get_ports {FMC_LA[17]}]
    set_property PACKAGE_PIN B18 [get_ports {FMC_LA_N[17]}]
    set_property PACKAGE_PIN D17 [get_ports {FMC_LA[18]}]
    set_property PACKAGE_PIN C17 [get_ports {FMC_LA_N[18]}]
    set_property PACKAGE_PIN A18 [get_ports {FMC_LA[19]}]
    set_property PACKAGE_PIN A19 [get_ports {FMC_LA_N[19]}]
    set_property PACKAGE_PIN F19 [get_ports {FMC_LA[20]}]
    set_property PACKAGE_PIN F20 [get_ports {FMC_LA_N[20]}]
    set_property PACKAGE_PIN E19 [get_ports {FMC_LA[21]}]
    set_property PACKAGE_PIN D19 [get_ports {FMC_LA_N[21]}]
    set_property PACKAGE_PIN E21 [get_ports {FMC_LA[22]}]
    set_property PACKAGE_PIN D21 [get_ports {FMC_LA_N[22]}]
    set_property PACKAGE_PIN B21 [get_ports {FMC_LA[23]}]
    set_property PACKAGE_PIN A21 [get_ports {FMC_LA_N[23]}]
    set_property PACKAGE_PIN B15 [get_ports {FMC_LA[24]}]
    set_property PACKAGE_PIN B16 [get_ports {FMC_LA_N[24]}]
    set_property PACKAGE_PIN F16 [get_ports {FMC_LA[25]}]
    set_property PACKAGE_PIN E17 [get_ports {FMC_LA_N[25]}]
    set_property PACKAGE_PIN F18 [get_ports {FMC_LA[26]}]
    set_property PACKAGE_PIN E18 [get_ports {FMC_LA_N[26]}]
    set_property PACKAGE_PIN B20 [get_ports {FMC_LA[27]}]
    set_property PACKAGE_PIN A20 [get_ports {FMC_LA_N[27]}]
    set_property PACKAGE_PIN C13 [get_ports {FMC_LA[28]}]
    set_property PACKAGE_PIN B13 [get_ports {FMC_LA_N[28]}]
    set_property PACKAGE_PIN C14 [get_ports {FMC_LA[29]}]
    set_property PACKAGE_PIN C15 [get_ports {FMC_LA_N[29]}]
    set_property PACKAGE_PIN A13 [get_ports {FMC_LA[30]}]
    set_property PACKAGE_PIN A14 [get_ports {FMC_LA_N[30]}]
    set_property PACKAGE_PIN E13 [get_ports {FMC_LA[31]}]
    set_property PACKAGE_PIN E14 [get_ports {FMC_LA_N[31]}]
    set_property PACKAGE_PIN A15 [get_ports {FMC_LA[32]}]
    set_property PACKAGE_PIN A16 [get_ports {FMC_LA_N[32]}]
    set_property PACKAGE_PIN F13 [get_ports {FMC_LA[33]}]
    set_property PACKAGE_PIN F14 [get_ports {FMC_LA_N[33]}]
    

    And I'm having this timing results


    By some reason hold is really bad, but I don't know if is a min delay error in calculations, or I have to put an actual input delay element to compensate.
    Clearly I've put a MMCM to generate the internal clock, that is 74.5 Mhz. I'm feeding Input delay elements with this generated clock, and a 200mhz reference clock. RTL is functional, but I want to address the timing issues to continue.

    schematic_ti.pdf

    The schematic is in that pdf.
    I have done the input delay computations using the formulas of figure 13, with 80msps data.

    Of course If I erase the constraints problems go away, but I can't check if there's enough slack to read data properly. Waveform seems of but I don't  know if there is enough window

    Hope you can help me

    Thanks

  • Alejandro,

    I will see if I can get one of our firmware experts to take a look at this. You can download example source code used by our TSW1418EVM from the link below. This board has a XC7A100T Xilinx device and is used to interface to our newer serial LVDS ADC's. See if this helps.

    Regards,

    Jim

     tidrive.ext.ti.com/.../90c1a88e-c9d4-45b9-aaae-b522f2c4b0c6

  • thanks jim, but this firmware package is apparently just for Serial LVDS ADC's. This is a parallel one.

  • Alejandro,

    You can find example Xilinx firmware that uses parallel LVDS data under the TSW14DL3200EVM product folder on the TI website.

    Below is Verilog/RTL used for parallel SDR data capture on another Xilinx platform. 

     

    wire [11:0]  adc_data_CHA; //12 SDR data bits for CHA

    wire [11:0]  adc_data_CHB; //12 SDR data bits for CHB

     

    reg [11:0] adc_reg_final_CHA;

    reg [11:0] adc_reg_final_CHB;

     

    always @(posedge adc_dclk) //Use the DCLK from ADC as clock. On rising edge of the DCLK.

    Begin

      adc_reg_final_CHA <= adc_data_CHA;

      adc_reg_final_CHB <= adc_data_CHB;

    end //On every rising edge of adc DCLK, store state of ADC data pins into a register (here for CHA and CHB). Modify accordingly.

     

    //always @(negedge adc_dclk) //This is a DDR implementation, so ignore if only using SDR. Stores state of ADC data pins on falling edge of ADC DCLK.

    //begin

    //  adc_reg_falling_CHA <= adc_data_CHA;

    //  adc_reg_falling_CHB <= adc_data_CHB;

    //end //Would need to append the rising edge data to the falling edge data in a register.

     

    assign adc_data_out_CHA = adc_reg_final_CHA;

    assign adc_data_out_CHB = adc_reg_final_CHB;

    You can then add an ILA debug core to monitor the adc_data_out_CHA net to observe the sample data.

    Regards,

    Jim   

  • I address the DDR part with the adequate primitive(IDDR), so that is not the problem. (In fact, it's pretty strange to don't use it in the reference design, despite in the SLAA545 application note an analogous DDR primitive for Altera FPGA is used).

    (here's the code, from 209 to 305)

    --------------------------------------------------------------------------	
    	generate_DDR_A : for index in 0 to 5 generate
    		IDDR_inst_A : IDDR
    			generic map (
    				DDR_CLK_EDGE => "OPPOSITE_EDGE",  			-- "OPPOSITE_EDGE", "SAME_EDGE" 
    				-- or "SAME_EDGE_PIPELINED" 
    				INIT_Q1      => '0',            			-- Initial value of Q1: '0' or '1'
    				INIT_Q2      => '0',            			-- Initial value of Q2: '0' or '1'
    				SRTYPE       => "SYNC")         			-- Set/Reset type: "SYNC" or "ASYNC" 
    			port map (
    				Q1 => ADC_DA_BUS_SDR(2*index),  			-- 1-bit output for positive edge of clock 
    				Q2 => ADC_DA_BUS_SDR(2*index+1),  			-- 1-bit output for negative edge of clock
    				C  => write_clock,              			-- 1-bit clock input
    				CE => dcm_locked_2,             			-- 1-bit clock enable input
    				D  => ADC_DA_BUS(index),        			-- 1-bit DDR data input
    				R  => inp_reset,                			-- 1-bit reset
    				S  => '0'  );                     			-- 1-bit set
        ADC_DA_INPUT_ctrl: IDELAYCTRL
        --------------------------------------------------------------------

    Also, the fact that the interface is center aligned is not addressed anywhere in the code (rtl or constraints)

  • Alejandro,

    Most of our firmware was done by a third party which no longer is used by our group for firmware development. I have offered you as much as I can regarding this. I would highly suggest you get in touch with the FPGA vendor for more help with this.

    Regards,

    Jim