ADC09QJ1300EVM: not enough output amplitude issue

Hi Muk,

For the second use case can you please confirm that the CPLL was locked? It can be checked by clicking the button below on the gui. The PLL will be locked and it will be green. Also can you confirm when the 

Also can you please make sure when changing RX_DIV setting TRIGOUT_EN is disabled and then enabled. 

Can you also try different sampling frequency may be 1G instead of 800MHz and see if you still see the issue. 

Regards,

Neeraj

Hi Neeraj-san

Thank you for your reply.

-After pressing the button in the EVM tag, They make sure that the PLL Status of the ADC PLL tag is green.
If the PLL Status is not green, the clock will not be output.
-When changing the RX_DIV setting, TRIGOUT_EN was turned OFF / ON, but the phenomenon was not improved.
・ I attach a waveform that was set to 1G aslo.

amplitude_problem.xlsx

The band of the oscilloscope used for the measurement is 300MHz, 2.5GS / s.
The probe is a 1GHz FET.

They found different test results, somtimes good, somtimes bad even if both 800Msps and 500Msps (1Gsps also)

Can they modify the output amplitude with GUI setting? Also, do you have any advice? 

Also, at Fs = 800Msps, the FPGA PLL locks when the amplitude is close to 500mV.
However, the data output of TI's JESD204 IP has not been confirmed.
Is there a way to check the output of the XILINX FPGA transceiver when using TI's JESD204 IP?

Thanks

Muk

 attached file

1205.amplitude_problem.xlsx

Hi

At Fs=500Msps、RX_DIV=64  Output frequency is 49MHz.

It is enough the bandwidth of oscope, right?

However, they have sometimes found the output amplitude issue with above condition.

(Question1)

Could you please test in your labo condition?

OnBoard 50M Ref, Fs=800Msps, JMODE10 and OnBoard 50M Ref, Fs=500Msps, JMODE10

RX_DIV = 16, 32 and 64

R234(DNP) J9 TRIGOUT+ side and R241(DNP) K9 RTIGOUT- side

(Question2)

Is it correct behavior that output amplitud was changed by GUI setting(change freqeuncy setting)?

(Question3)

They want to check the output from gtx_8b10b_rxtx in the JESD204 IP

They try to modify teh cooding as below,

(* mark_debug = "true" *)     output  [31:0]  gt0_rxdata_out,

However, they cannot see the data.

Is there any method of checking the output from gtx_8b10b_rxtx in the JESD204 IP?

They are considering teh debugging method.

Thanks

Muk