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Original question:

ADS7844: ads7844 busy signal

ADS7844: SPI Bus Question

Mike Yu
Intellectual 2310 points
Part Number: ADS7844

Hi Team,

We have some questions for the SPI behavior during working with the customer. The waveform below is capture from the ADS7844 SPI bus.

  1. We noticed the waveform is changing state on different edge of the clock signal (red rising edge & yellow dotted failing edge)
  2. Din control bit is being send to ADC while ADC is still BUSY – acceptable ?
  3. tBD data sheet spec max 100ns vs measured tBD (A waveform) is 200ns
  4. tCSS data sheet spec min 50ns vs measured tCSS (A waveform)is 0ns

Any idea how ADS7844 will respond to such waveform, we are getting very intermittence failure (consistent failed on certain channel, and not able to repeat the failure when we tested several days later), we would expect the failures to be more consistent, could you please kindly advise on these? Thank you.

Best regards,

Mike

  • 0
    TI__Mastermind 25020 points

    Hello, 

    Overall, I question the integrity of the SCLK signal. The scope shows quite a large spike. The clock not settling could cause communications issues. 

    Would you share what method of conversion timing you are using, example 16 SCLK, 24 SCLK, or 15 SCLK per conversion?

    1. BUSY will go low when the control bits are being read and when a conversion is taking place. Frame B in yellow is correct. Frame A in red though likely means that the device did not read the first bits of data frame of the control bits. If the device is not reading the control bits correctly, this could be the reason why the device is not responding as expected. 

    2.  I see that before CS goes low, BUSY seems to be idle, I would suggest pulling this pin high with a pull up resister.  Note that BUSY is active low, thus once CS is pulled down, BUSY should enable. 

    3.  I am not sure where you are measuring 200ns, but note that this would be measured on yellow frame B in your picture

    4.  I suggest having SCLK held low when CS transitions low, then within the timing requirement bring up the clock. 

    Regards

    Cynthia

  • 0 in reply to Cynthia
    TI__Intellectual 2310 points

    Hi Cynthia,

    Thanks for support on this.

    Best regards,

    Mike