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Original question:

ADC128S102: Power Down VA vs SPI Bus

ADC128S102QML-SP: Digital Interface Asserted Before VD

Jim Gavin
Intellectual 920 points

Part Number: ADC128S102QML-SP

I am designing in the ADC128S102QML-SP for a space application and I am working on designing it to ensure that VD never comes up before VA. With that, there are some other details I must consider. Specifically, the digital interface. The datasheet section 7.3.3 Digital Inputs and Outputs states that the inputs "... may be asserted before the digital supply (VD) without any risk." This is confirmed in the ADC128S102: Power Down VA vs SPI Bus E2E post. However, the reply indicates that the digital inputs must not violate the recommended operating conditions. I'm assuming this means not violating the Absolute Maximum Rating of VA+0.3V for the voltage on any pin to GND. Is this a correct interpretation of the reply in that post?

Additionally, the ADC128S102: Power supply design E2E post seems to conflict what the datasheet states in section 7.3.3 by effectively stating that the sources of the ADC digital interface inputs must be Hi-Z if VD is unpowered. Is this incorrect?

The use case that I'm considering is where VA is powered to 5V, VD is at 0V (floating) and SCLK, DIN, and \CS are at 5V. Will this cause any issues? I expect not since the digital inputs will be less than VA+0.3V, so the ESD diode between VD and VA will not conduct. Is this a correct understanding?

  • 0
    TI__Mastermind 25070 points

    Hello,

    Your interpretation is correct. The abs max should be followed at all times. Your use case should not cause any issues. 

    In the E2E post you referencing, I believe the TI engineer was alluding to the fact that the original post had VA and VD tied together. This meant that if the digital bus was exceeding VD, this case, it would also be exceeding VA, thus he added that note to highlight the abs max limitation. 

    Regards

    Cynthia