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Original question:

OPA4171: Effect of capacitor in feedback loop-OPA4171

ADS8556: Circuit configuration and front end

Sunney Kumar
Prodigy 190 points
Part Number: ADS8556
Other Parts Discussed in Thread: OPA171

Hi,

We are using two ADS8556 in serial interface (not in daisy chain). I have following questions on front end and circuit configuration:

  1. For front end where signal frequency is up to 4.4KHz (including Harmonics), non-inverting configuration is used. From stability point of view, there are two circuits one with CF and without CF. The phase margin with both circuits is above 45 deg (for stable op PM >=45deg). However, with CF PM increased to 81.9deg. Do you recommend using CF as it will increase PM to 81.9deg? Please confirm. (Refer below image)
  2. Input signal to above circuit is the output of voltage/current sensors, does non-inverting configuration help in achieving high input impedance? Is it required?
  3. Generally non-inverting configuration is more prone to stability issues and CMRR of configuration is also not good.
  4. Is inverting configuration required here? as recommended in application circuit in datasheet.
  5. We have two ADCs (ADS8556), their BUSY signal is monitored using diode ORing. I saw in one of the posts which says it is not recommended and suggestion is to use OR gate? Can you explain why?
  6. For hardwire based configuration, what is the recommended values of pull up or pull down resistors?
  7. In datasheet 49.9 and 370pF is used on analog inputs which provides Fc = 8.6MHz and RC = 18ns. Datasheet further mentions that this RC will reject high frequency noise and meet settling requirements as well. What is the settling time requirement? It will help me to choose appropriate values for RC.

Regards,

Sunney

  • 0
    TI__Mastermind 25030 points

    Hello, 

    The first four questions seems to be related to the op amp circuit, I will defer to op amp team to continue support for these. 

    I suggest reading through TIPL: Op Amp Stability, Phase Margin ~click here~. 

    5. The BUSY signal is usually monitored by a host device to know when/if either of the device is in an ongoing conversion, an OR gate will have performance advantages over a diode 

    6. A pull up resistor of 10k to 100k would be recommended.

    7. This device is a SAR ADC, it is composed of a switching capacitor, the input capacitor, which in this device is 10pF or 20pF based on the range used. The Cin needs to be charged within the tacq time by the op amp and  external RC, which is a minimum of 280ns, at the fastest sampling rate. Note, this time does not take into affect the time between channel samples that the Op amp has to charge the RC circuit. The settling requirement thus is based on the sample rate the device is being used. 

    What sampling rate will you be using the device? 

    Regards

    Cynthia 

  • 0 in reply to Cynthia
    Prodigy 190 points

    Hi,

    Thank you for your response.

    5. Ok. 

    6. Ok

    7. I am checking on the sampling rate with the team, meanwhile can you please let me know what is the relation between t.ACQ and sampling rate. since minimum t.ACQ is 280ns, I believe that is for maximum sampling rate 450 kSPS.

    Also for questions 1-4, I am including updated simulation as in the last simulation I hadn't included the load capacitance and series resistance.

    Regards,

    Sunney

  • 0 in reply to Sunney Kumar
    TI__Mastermind 25030 points

    To learn more about SAR ADC, i suggest going through TI Precision Labs: Basic Operation of SAR and Delta Sigma ~click here~, it is a video series covering this and other topics, the power point is also available. 

    Overall, to complete one conversion, the device goes through a Taqc phase and Tconv phase, These two times added up to one conversion time (1/sampling rate).  thus you are correct that at the max speed, this will be using the minimum acquisition time of 280ns. During the acquisition time, is when the input drive circuit, the OPA171 will have to drive the input signal. The longer time available, the better. 

    with an input of 4.4kHz, I assume you will be sampling at a minimum of 10Khz. 

    I would suggest 15Kohm resistor and a 400pF cap

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Prodigy 190 points

    ok thank you Cynthia, I will go through the links you have suggested.

    For front end related questions do i need to post it on amplifier fourm or some body will answer here.

    Regards,

    Sunney

  • 0 in reply to Sunney Kumar
    TI__Mastermind 25030 points

    I will reassign this thread, and they will be notified, thus they should follow up here

  • 0 in reply to Cynthia
    TI__Mastermind 33081 points

    Sunney,

    1. For front end where signal frequency is up to 4.4KHz (including Harmonics), non-inverting configuration is used. From stability point of view, there are two circuits one with CF and without CF. The phase margin with both circuits is above 45 deg (for stable op PM >=45deg). However, with CF PM increased to 81.9deg. Do you recommend using CF as it will increase PM to 81.9deg? Please confirm. (Refer below image)

      Increasing the PM is a design consideration based on what you would like to achieve out of the circuit. If both are above 45 degrees phase margin then both should safely be stable, however the more phase margin you have, the less overshoot you will have and the longer it will take to settle. Please note that you should also consider your load capacitance when you are doing your stability calculations, as this can greatly impact your stability.
    2. Input signal to above circuit is the output of voltage/current sensors, does non-inverting configuration help in achieving high input impedance? Is it required?

      Your input impedance in non-inverting is going to be the input impedance of the non-inverting terminal, which is very high. Depending on what is considered high impedance from your sensor, you can also have it on your inverting terminal if your feedback resistors are appropriately sized.

    3. Generally non-inverting configuration is more prone to stability issues and CMRR of configuration is also not good.

      See above comments on making inverting terminal higher impedance.

    4. Is inverting configuration required here? as recommended in application circuit in datasheet.

      Inverting configuration is chosen (I believe) because it's far simpler to set your common mode voltage and ensure it's within the acceptable range.

    Best,
    Jerry