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Hello,
I am using custom board which has an interfaces of DAC (DAC3283 ) and Clock Synthesizer (CDCE62005).
For DAC it is 16 bit with 800MSPS DAC output and 8-Bit Input LVDS Data Bus .
I need to give 8 pair of differential input D[7:0]P/N .
My doubt is whether i need to separate input data as I and Q before given to a actual DAC input OR can i give direct differential pair dac input using DDS compiler with OBUFDS ???
Hi,
I do not understand your exact question. I believe you are asking about Xilinx FPGA implementation, which can be found in the following link:
https://docs.xilinx.com/v/u/en-US/xapp594-parallel-lvds-hs-dac-interface
The expected LVDS bus input can be found here:
