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ADC3660: FCLK duty cycle is not 50%

Part Number: ADC3660

I'm using the ADC3660 to sample some data at 25 MSPS. I'm trying to get the command/clock interface running with my FPGA, and I can reliably write/read the registers in the ADC. I'm trying to use the following settings.

  • Sample rate: 25 MSPS
  • Output Mode: 2-wire decimation bypass, 16 bit resolution
  • Sample Clock: Differential
  • Voltage Reference: External 1.6V

I'm running the following function with the soft core processor in my FPGA. write_a2d_spi(destination,value) write's "value" into the "destination" register in the ADC. I have confirmed that I can read back the values that I wrote, so I'm confident I'm commanding it properly.

u32 configure_ti_a2d(void)

// refer to TI 3660 datasheet, section (Configuration Example)
write_a2d_spi(0x7, 0x4b); // 16-bit, 2-wire

write_a2d_spi(0x13, 0x01); // load efuse step 1
usleep(1000); // wait 1 ms
write_a2d_spi(0x13, 0x00); // load efuse step 2

write_a2d_spi(0x0A, 0x7F); // configure CMOS output buffer step 1
write_a2d_spi(0x0B, 0xEE); // configure CMOS output buffer step 2
write_a2d_spi(0x0C, 0xFC); // configure CMOS output buffer step 3

write_a2d_spi(0x18, 0x10); // enable DCLKIN

write_a2d_spi(0x1B, 0x08); // select 16-bit resolution
write_a2d_spi(0x1F, 0x50); // enable DCLKIN and DCLK output Buffer

return 0;


I haven't implemented any logic to decode the data coming from the dA5/6 and dB5/6 channels, but I see data on them and I see what I would expect from DCLK and DCLKIN with my logic analyzer (both 100 MHz). However, FCLK seems to be high for half a clock longer than expected. I verified this on the oscilloscope which measures FCLK duty cycle at ~62%.

Theoretically, as long as a new word starts on the rising edge of FCLK, I can just count DCLK and use that to keep track of the start and each data word, but I'm wondering if I did something wrong in the configuration of the ADC to change the duty cycle of FCLK. I'm trying to read back a constant test pattern with my logic analyzer, and I'm only seeing the test pattern in the first 16 bits of every FCLK cycle, and then the next 16 bits seem to be something totally different, so that leads me to believe something isn't set up right.

Is there a command or setting I can send to change the FCLK duty cycle to 50%? Is this a sign of other issues?

  • Hi Ryan,

    I am checking into this and will get back to you soon.

    Regards, Amy

  • Hi Ryan,

    I set up the ADC3660EVM in the lab and configured it as you describe. I measured the FCLK duty cycle to be 50%. Can you read registers 0x20, 0x21, 0x22? These are the registers responsible for setting the FCLK duty cycle.

    Regards, Amy

  • Amy, thanks for your response. Here's what I'm getting from these registers:

    0x20: 0x00

    0x21: 0xFC

    0x22: 0x0F

    The datasheet seems unclear about what values in these registers correspond to what duty cycle. It says in decimation bypass mode the FCLK pattern gets adjusted automatically for the different output resolutions, so I didn't do anything with it. It looks like it's currently using the reset value.

  • Amy, I found the issue. I needed to enable the MAPPER EN bit in register 0x1B to enable changing the resolution to 16 bits. Writing a 0x88 instead of 0x08 fixed the issue. Thanks for your help.

  • Hi Ryan, 

    Thanks for following up. The reads you saw from registers 0x20, 0x21, 0x22 matched what I was seeing on our ADC3660EVM in the lab. I checked the read from register 0x1B for this mode, and 0x88 is correct - it sets the mapper EN bit for configuring the part bypass mode. Glad you found the issue, we always appreciate hearing the feedback.

    Regards, Amy