ADC12DJ3200: Phase synchronization between 2 ADCs

Part Number: ADC12DJ3200
Other Parts Discussed in Thread: TIDA-01022, LMK04828, LMX2572, TIDA-010122, TSW14J57EVM, TIDA-01028

Hi,

We have a custom board with 2 ADC12DJ3200 ADCs and Kintex UltraScale FPGA from Xilinx. We are using JMODE 11.

The data captured from both the ADCs (4 channels) is fine, w.r.t FFT, SNR, SFDR etc. But the phase difference between the ADCs is high, and not consistent.

Within the channels of the same ADC, phase synchronization is fine, but we are not able to achieve that between the ADCs.

It will be of great help if you could help us with suggestions.

Thanks!

  • Ayana,

    In the Technical Documentation section of the product folder on the TI website, click on the following for help with multi-device synchronization:

    Step-by-step considerations for designing wide-bandwidth multichannel systems

    Regards,

    Jim

  • Hi Jim,

    We had gone through the link shared by you.

    Our Front end circuit is almost similar to TIDA-01022 (https://www.ti.com/lit/df/tidrut6/tidrut6.pdf?ts=1655890149698)

    For clocking, we are using  LMK04828, LMX2572 and all the clocks are length matched.

    ADC sampling rate is 3200MSPS and NCO frequency we have set as 1000MHz. 

    The FPGA design is created as per this article:

    Guidance when using multiple JESD RX Cores

    Thanks & Regards,

    Ayana

  • Ayana,

    Have you tried using the TI JESD204B/C free IP instead of Xilinx?

    You can request the free TI JESD204 rapid design IP by going to the following link:  https://www.ti.com/tool/TI-JESD204-IP.

    Currently the JESD204 rapid design IP supports the following FPGA families:

    • Xilinx® Virtex UltraScale and UltraScale+
    • Xilinx Kintex UltraScale and UltraScale+
    • Xilinx Zynq UltraScale+ and Zynq UltraScale+ (Auto)
    • Xilinx Artix 7 and Artix 7 (Auto)
    • Xilinx Virtex 7
    • Xilinx Kintex 7 and Kintex 7 (Auto)
    • Xilinx Zynq7000 and Zynq7000 (Auto)

    Included with the IP is documentation and example reference designs to allow the user to get up and running quickly.

    Regards,

    Jim 

  • Thanks for the suggestion, Jim.

    But our customer needs the design using Xilinx IP.

    Regards,

    Ayana

  • Hi Ayana,

    Regarding the multi-channel analog front end synchronization, can you confirm all the JESD204B complaint clocks to multiple ADCs are aligned (DCLKs and SYSREFs)?

    Most of the multichannel RF-sampling front end receivers reference designs (TIDA-01022, TIDA-010122, TIDA-01028, etc..) were used TI JESD204 capture card (FPGA board) TSW14J57EVM and validated sync performance.

    Regarding the digital features of ADC synchronization, I would be suggesting to go over the TIDA-010122 reference design design guide using the same TIDA-01022 hardware, which has some detailed guidance for it.

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Ajeet,

    All the device clocks and SYSREFs are aligned.

    Automatic SYSREF Calibration is done and SRC_DONE bit is high, so we assume setup and hold time requirements of SYSREF relative to the device clock are met. After the SRC_DONE bit is high, is it required to clear SRC_EN bit of SYSREF Calibration Enable register?

    SYNC signal from both the JESD RX IPs is ANDed and then given to the ADCs as suggested in the reference design.

    We are not sure how to choose proper elastic buffer release point. When we read the RX buffer adjust register (of Xilinx JESD204 RX IP), the values returned for each lane is different every time. This register indicates the maximum allowable reduction of the latency for each lane. From the reference design shared also, we didn't understand how to choose the release point. Requesting your support on this.

    Thanks,

    Ayana

  • We also tried without automatic SYSREF calibration. We read the SYSREF_POS register values in order to write to SYSREF_SEL. But the SYSREF_POS values are not consistent, the SYSREF_SEL calculated using SYSREF_POS register values keeps changing always.

  • Hi Ayana,

    Can you please make sure your sysref and clock signal are stable and source syncronous with each other. 

    Regards,

    Neeraj 

  • Hi Neeraj,
    We are not able to measure the device clock on scope, however we simulated and calculated the timing diagram of ADC device clock and SYSREF clocks. The details of clock distribution and timing diagram is attached herewith (refer ADC_Dev_clock_sysref.pdf). Let us know if there is any other method to validate the clock alignment.
    We have observed a variation in SYSREF signal in FPGA in chipscope/ILA (refer sysref_capture.jpg ) though the actual signal when probed using oscilloscope is fine. Let us know whether it will cause any problem.
    Thanks,
    Ayana
  • Hi Ayana,

    Can you please remind of your JMODE sampling frequency and K value used for the ADC? 

    I am trying to see if SYSREF frequency is correct? 

    Regards,

    Neeraj

  • Sure, Neeraj.

    We are using JMODE 11, sampling frequency 3200MHz, K = 32 and SYSREF = 3.125MHz.

    Regards,

    Ayana

  • Hi Ayana,

    Can you please provide me your register writes. Also can send me your schematic for ADC and clock for the ADC. 

    Can also program register address 0x29 to 0x60 and then read the SYSREF_POS register(0x2C-0x2E) 10 time and send the results. 

    After that program address 0x29 to 0x70 and then read the SYSREF_POS register(0x2C-0x2E) 10 time and send the results. 

    Regards,

    Neeraj