Part Number: TSW1400EVM
I have been using High Speed Data Converter Pro with a TSW1400 and AFE5803EVM to capture data. I have been using an external 10MHz clock from the TX7316EVM CLK_10M_OUT SMA connector. In the AFE5803EVM GUI, I leave the clock set to differential. On the AFE5803EVM, I have moved both JP9 jumpers to use the external ADCLK from J15. This configuration has been working fine for me on two different board sets until I recently damaged my AFE5803EVM and had to order a new one. I have now tried two different replacement AFE5803EVM boards with both of my TSW1400's, and I consistently get an error that says "Frame clock error in Read DDR to file".
I have confirmed that the 10MHz clock is getting onto the AFE5803EVM board. The voltage levels at the center post of JP9 range between 0.49 and 1.48V, which is above the typical 0.7V swing listed in the AFE5803 datasheet for AC coupled LVDS clock. I also observe that the TSW1400 USER_LED4 is on, indicating that the clock is being received.
As part of my debug process, I switched to the 40MHz on-board clock, changed JP9 jumpers back to original settings, set the AFE5803EVM GUI to single ended clock input and changed the HSDC Pro clock setting to 40M. Having done all this, I was able to capture data without the Frame clock error. At this point, I switched everything back to the external 10MHz clock with the system under power, and I was able to capture data. However, the data didn't look real as it swung wildly from min to max scale.
The only other changes to the AFE5803EVM are that JP15 has been moved for external VCNTL input from J14, and R102 has been removed to allow a DAC with moderate output resistance to directly drive J14. The removal of R102 didn't happen before I first powered up the board, so the 49.9 ohm resistor was overloading my DAC at first, but I get the same results with or without R102 installed.
In the current test case, the TX7316 is not triggering, so the inputs to the AFE5803EVM are floating. I have the AFE5803EVM GUI configured for 24dB LNA gain, I am enabling the extra active loads with 3600 ohms to approximately match my 500 ohm source impedance. However, since I am not triggering the TX7316 (CPLD firmware modified), there is currently no connection to the source.
In summary, with the 40MHz internal clock, data capture works and the data looks reasonable for floating inputs with active termination. With the 10MHz external clock, I get a "Frame clock error in Read DDR to file" error. I can trick the system into not giving this error, but then the data is erroneous.
