DAC37J84EVM: Xilinx ZCU102 with this DAC

Rory,

What FPGA source code do you plan on using? Whatever code you are using, you must have the FPGA pin that is connected to the SMA you plan on using for SYNC assigned properly. Everything else should be good as is.

Regards,

Jim

Hi Jim

Thanks for your reply.

The source code I am going to use is for KCU105 and DAC38RF82, which can be found from the description website of the DAC38RF82. I am wondering why I have to use an additional SMA for SYNC, are there are spare pins in the FMC that I can directly use?

Also, when I look into the schematic of the DAC37J84EVM I noticed that the output is actually transformer coupled with Impedance ratio 2 :1. According to the datasheet of DAC37J84 (7.3.29) can I regard it as a voltage output between -0.5 and 0.5 V if the output load is 50 ohm?

Kind regards

Rory

Rory,

This was a mistake made by Xilinx. They forgot top route the SYNC to the dedicated pin on the FMC connector that is called out by the VITA spec for JESD204B standard.

Regards,

Jim

Hi Kim

Thanks for the clarification.

Could you also look into the schematic of the DAC37J84EVM as I mentioned before? I am wondering what kind of output it looks like in terms of the voltage or current. I ideally I want to have the voltage output, since it has transformer before the SMA, I assume the output would be voltage from -0.5 to 0.5 V?

Rory

Rory,

At full gain, the output will be -0.5V to 0.5V.

Regards,

Jim 

Hi Jim

Thanks for your reply.
Is it possible to output voltage between -0.1 and 0.5 V, without centering in the 0 V?

Rory

Rory,

What are you interfacing the DAC to? See if the attached articles help.

Regards,

Jim

6471.DAC to Op Amp Part 2, Current-sourcing DACs slyt360.pdf1526.DAC to Op Amp Part 3, Current-sourcing DACs slyt368.pdfDAC_Source_to_Op_Amp_Wksht_Part3.xls