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Original question:

ADS8332: Basic question

ADS8332: Basic question about sample rate

Takumi Suzuki1
Mastermind 8610 points
Part Number: ADS8332

Hi,

I would like to ask you a question about the setting of sampling rate.

In case of using "default setting", that is to say, CFR register is "FFF"h setting,

the sample rate is determined by "CONVST" signal timing.

For example, to realize 500KSPS sampling rate, we should set the timing of CONVST around 1.9uSec, right?

(1.9uSec = 21xCCLK(11MHz))

Thank you for your support!

Best Regards,

Takumi

  • +1
    TI__Mastermind 46090 points

    Hello Takumi-san,

    Using the default settings, the ADC will use the internal oscillator, which has a minimum frequency of 10.5MHz, or a clock period CCLK of 95.24ns.  This equates to a maximum cycle time of 21*CCLK=2uSec.

    Yes, in order to realize a sample rate of 500ksps, you need to apply a CONVST signal with a minimum period of 2uSec.  If CONVST period is less than 2uSec, then you may get incorrect readings since some ADCs will require up to 2uSec to complete the cycle.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Mastermind 8610 points

    Hi Keith-san,

    Many thanks for your reply !

    Regards,

    Takumi