Help needed
We have made a board 8 x ADC3600 with a FMC connection, connected to a Xilinx AC701
The first ADC3660 has the FCLK, the other 7 are data only
When I grab data from the first ADC3660 - it looks good
The other ADC3660 return good data, but only after a bad read of data. I.e., in the data stream in the HSDC pro - If I use 4 channels, 2 of the channels will be rubbish and 2 good (2 channel mode = just rubbish, yet okay on the first ad3660 with the FCLK)I
Xilinx build
My issue is, it that I would now like to read data from all the ADCs at once.
The example build has an option ADC_L in the ADC if IP block. This builds okay, but I'm not seeing the data correctly, plus it gives a small timing error.
It looks like the data isn't being written to BRAM correctly.
I also added in the ‘Sync’ option, but that doesn’t seem to do anything. How should the chips be synchronised together?
Also:
On the clock, the data sheet says common mode voltage of .9 but when AC coupled, we have a common mode voltage of 1.1 – which is the same as the EVM board. I admit it seems happy as it is.
Many thanks
