I am creating a bus functional model of the ADS1258 in VHDL, and in trying to model the initial delay from rising edge of conversion start to first stable data versus the subsequent delays, I am getting a model that appears as though the time to first data is actually shorter than the subsequent data rate for continuous conversions.
I think the problem is that the DLY[2:0] (switch-time delay) is not incorporated into the values in Table 11 because it says DLY[2:0]=000.
I am using an external 12.5MHz clock and using autoscan mode, DR="10" and DLY="011", so that my data rate calculation is:
12.5MHz / (128 * (4^(3-2) + 4.265625 + 4)) = 7961.78 Hz, the denominator is1570 tclks (12.265625 * 128 tclks)
But my value from Table 11 for DR="10" and IDLMOD=0 (wake from standby) is 1092 tclks.
1092 < 1570 means my initial delay is shorter than my continuous sampling delay, which is contrary to the drawing in Figure 56.
Perhaps I am missing something big here, like Table 11 value needing to be multiplied by 128? Please advise. Thanks!