TI-JESD204-IP: How to package TI204C-IP as IP that can be used outside reference design

Hi Keira, one of our experts will reach out soon regarding this. Kindly await a response.

Regards, Chase

Hi Keira,

The TI JESD IP is built to meet the JESD standard, and the reference designs are provided as examples of how the IP can be configured for a particular LMFS mode. There is not automatic way to translate this to the mode of the converter. I am listing the steps below:

1> The transceiver IP needs to be edited based on the lane mapping and reference clock setup of your particular application. This needs to be done through the transceiver wizard, but you can open the transceiver xci of the reference design as a comparison point for edits. Unfortunately, there is no other way to address this, because the transceiver generation is strongly controlled by Vivado. If your changes result in a modification of the transceiver entity, then the transceiver wrapper (gtx_8b10b_rxtx.sv) file needs to edited to address this. This is explained in section 6.1 of the user guide. This is also the reason that the transceiver wrapper is the only module in the JESD IP that is left un-encrypted.

2> The rest of the TI JESD IP needs to be parametrized to meet the LMFS requirements of the JESD link. Once again, the reference design can be used as a guide, but it addresses a specific LMFS mode that may not match the one that you have selected. The ports and parameters are described in the user guide, but often it is possible to modify just the jesd_link_params.vh file of the reference design to set the parameters of interest.

3> Finally, the lane data output of the JESD IP needs to be mapped to samples. The formatting of the data on the lanes is described in section 6.5 of the document.

I hope this addresses your queries. The TI JESD IP implements the JESD specific protocols with two specific requirements:

1> It is parameterized to match the JESD link of the converter that it is interacting with

2> The transceiver (SERDES) of the FPGA is set up to lock into the data streams and feed the extracted data to the IP (so that it can implement its protocol).

The two aspects above need to be customized by the user for the specific application case. The reference designs have been provided as guidance points for this process.

Regards,

Ameet

Ameet,

Thank you very much for your help. Your explanations help me quite a bit. When you say package the top level as an IP, do you mean the top level of the ref design (TI_204c_IP_ref) or the hidden top level? I am assuming you mean the hidden top level.

Thank you,

Keira

Actually, I am very unsure of what files to include when building the project to package it into IP rather than running the reference design. Since my goal is to use this IP with the ADS54J64, I do not need any of the TX logic for connecting to a DAC.

Hi Keira,

Sorry for the delay. Ameet is out on travel last week and this week as well.

He will address this once he is back.

Regards,

Rob

Hi Keira,

I will recommend creating a wrapper around the JESD IP core and packaging that wrapper. You will need to create a wrapper to help define the JESD IP parameters and to implement the logic for the lane to sample mapping (as explained in my first response). 

The TX pins will not get connected to your wrapper ports, because you don’t have a DAC in your system. One your set the JESD IP parameter to RX instead of RXTX, the Tx related logic will automatically get optimized out. 

Regards,

Ameet 

Hi Ameet,

Can you be more specific? Below is a screenshot of the example project set up. I believe I should only keep the hidden svp file and everything below it but when I remove TI_204c_IP_ref from the project, jesd_ip_gen.genblk1.j8b10b_inst and all its children get removed from the project as well. Since I cant open, view, or edit the hidden file, I am not sure how to fix this. I usually code in VHDL so maybe I am missing something in the verilog TI_204c_IP_ref.sv but I do not see why removing that file removes jesd_ip_gen.genblk1.j8b10b_inst from the design. 

Also, for reference, I started another forum post on the topic of getting this working here: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1158213/ti-jesd204-ip-modifying-ti204c-ip-and-figuring-out-clocks-for-the-ads54j64-and-ip/4356689

Maybe you can help on that post too since the no one has responded to most of my questions.

Thank you,

Keira

Closing this post as it appears there are two open posts with the same issue.

Hi Keira,

Perhaps I have misunderstood your question? The TI JESD IP core (svp) file is an instance in the reference design. If you remove the reference design, you will need to replace it with another that instances the IP. I am not sure if Xilinx permits an encrypted file to be set as the lop level instance, because even if it did, you wouldn't be able to edit the parameters. This is probably what causes the 8b10b sub-module to get removed as well.

Regards,

Ameet

Please do not close this post. I have a related post but its not the same.

Ameet,

Thank you for your explanation. That makes sense. I shared the picture so that you could use the names of the actual files in your explanations to prevent further confusion. I will modify the top level file TI_204c_IP_ref to remove the other unneeded instantiations like the VIO, rx_refdesign, and tx_refdesign for packaging this as IP. I think this is so confusing because I cannot see the hidden file at all, which means I have to assume that how its instantiated in the TI_204c_IP_ref does not need to be modified, even though I am modifying a child of the hidden file through the transceiver wizard. 

My last question for this thread is with the modifications I am making to j8b10b_xcvr through the transceiver wizard, does Vivado automatically update the hidden parent file or are there no changes to that hidden file no matter what is changed in the transceiver wizard? I ask because one of the things I changed in the transceiver wizard is disabling the TX. I would assume this would change the ports of the core, but maybe they stay there and are just not connected to anything?

Here is a picture of the hierarchy and transceiver wizard for reference. 

Keira