ADC32J45EVM: Using the ADC32J45EVM with KCU105

Hi Jim,

I followed the steps in the powerpoint and used that .ini file, but I get an error. The error is "read DDR to file TIMED_OUT_ERROR time out error". All the other steps worked fine.

Lucas,

Per the last slide in the document I sent, "If there is a time out issue, reload the firmware, reconnect HSDC Pro, and try capturing again". Did you try this?

Regards,

Jim

That did not work, same issue every time. What is the source of the sample clock in this demo? It looks to me like the external clock input. The .ini file you provided was for the 34j45, not the 32j45. Could that be related to the issue?

Lucas,

The setup uses internal clock mode on the ADC32J45EVM. We think the issue is with the ini file. We are working on creating a new one for the ADC32J45.

Another option for you is to try this interface using free TI204C-IP. You can request this IP by going to the following link: 

https://www.ti.com/tool/TI-JESD204-IP.

 This IP comes with instructions and examples. Currently the JESD204 rapid design IP supports the following FPGA families:

• Xilinx® Virtex UltraScale and UltraScale+
• Xilinx Kintex UltraScale and UltraScale+
• Xilinx Zynq UltraScale+ and Zynq UltraScale+ (Auto)
• Xilinx Artix 7 and Artix 7 (Auto)
• Xilinx Virtex 7
• Xilinx Kintex 7 and Kintex 7 (Auto)
• Xilinx Zynq7000 and Zynq7000 (Auto)

Regards,

Jim

Thank you. That JESD IP looks very promising. I will try to use that.

Lucas,

The original firmware was provided by Xilinx many years ago. They are no longer supporting this. We do not have a working ini file for the ADC32J45 and probably will not get one. I would suggest you pursue using the TI IP or contact Xilinx for help if you plan on using their IP.

Regards,

Jim