I have a system with 3x ADS1282 ADCs. I need them all to sample at the same instance. They all share a /PWDN, /RESET, and SYNC signals from an MCU. These also all use buffered copies of the same 4.096MHz clock.
They are all powered up together, and the first thing I do is to set set the /PWDN pins high. Then I pull /RESET low for 50uS, then set it high again. Finally, I set SYNC high.
After they are out of reset, I can see the /DRDY lines toggling at the default 1kHz sample rate. Once I set SYNC high, though, the chips will sample 1 or 2 more times, then /DRDY just stays high. Sometimes they continue to run fine. Almost always when I set SYNC high, 1 or 2 of the ADS1282 chips stops sampling... Each time I run it its a different 1 or 2 ADCs.
I have verified 3.3V power is good and stable. 4.096 MHz CLK in is stable. I am also able to program them to run at different sample rates, so the SPI interface is good.