SYNC pulse in Pulse Sync Mode - RDATAC

Hi Daniele,

Figure 46 shows SYNC going high-low-high primarily to include the timing information about the minimum SYNC pulse width (tSPWH and tSPWL). However, during normal use the SYNC signal is taken high to synchronize the ADC. SYNC is returned low sometime later (either soon after performing synchronization or prior to the next synchronization - the falling edge of SYNC doesn't perform any action so the timing of this edge is not critical so long as the the minimum SYNC pulse width timing specification is met).

Here is an example waveform (though the pulse width here is much wider than it needs to be):

Please note that the timing of the SYNC rising edge is important. The datasheet recommends at least a 10 ns setup time between the SYNC rising edge and the CLK rising edge. If this setup time in not met then the device may ignore the SYNC pulse and continue on-going conversions.

• To avoid this issue, it is best to align the SYNC rising edge with the CLK falling edge. This can done using a flip-flop to re-clock the SYNC signal (a discrete solution could use something like the SN74HCS72, D-type negative-edge-triggered flip-flop).
   
• Alternatively, if the SYNC and CLK signals are asynchronous, then I would suggest toggling the SYNC signal multiple times (similar to what is shown in Figure 46). It is generally a low probability for the SYNC and CLK signals to align when running asynchronously, and the probably of this happening two times consecutively is significantly lower, so toggling the SYNC pin twice is usually sufficient to ensure that synchronization occurs.

Best regards,
Chris