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DAC38RF84: DAC PLL requirements

Part Number: DAC38RF84
Other Parts Discussed in Thread: LMK04828

Hi, 

I am using the DAC38RF84 in my design and when I read the status register, I am getting a high bit at bit 0 of status register 0x05. This makes me understand that the internal PLL is unlocked. I wonder if somebody can provide me information on the requirements of proper functioning of the DAC and especially the internal PLL.

For more clarity this system uses LMK04828 as the clock source for the DAC and FPGA as the controller. The system is proven and made in multiple quantities and are functioning. But in a recent build the above status is observed. I strongly suspect there is some error happening in the circuit build or some other specific problems to the build.

Kiran

  • Kiran,

    What are your PLL settings? Did you tune the PLL to lock the VCO? What is your PLL target frequency and what is your reference frequency?  Section 8.4.2 Internal PLL/VCO of the data sheet provides information regarding your question.

    Attached is an example of setting up the PLL using the DAC38RFxxEVM GUI. 

    Regards,

    Jim

    6064.DAC38RF89_real_821_PLL.pptx