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ADS131A04: Status Bits in response are 0x2220

Roy Wengler
Intellectual 405 points
Part Number: ADS131A04


Hi,

we use the ADS131A04 in our design and it work. But in every conversion result the status bits are 0x2220 ... Why ?

Here my initialisation 100: (M0 Vdd | M1 and M2 GND -> 24 Bits)  

ADS131A04_Unlock()
ADS131A04_Reset()
ADS131A04_Unlock()
ADS131A04_ReadReg(0x00)
ADS131A04_WriteReg(0x0b, 0x78)
ADS131A04_WriteReg(0x0c, 0x32)
ADS131A04_WriteReg(0x0d, 0x02)
ADS131A04_WriteReg(0x0e, 0x25)
ADS131A04_WriteReg(0x11, 0x00)        // ADC1 Gain 1
ADS131A04_WriteReg(0x12, 0x00)        // ADC1 Gain 4
ADS131A04_WriteReg(0x13, 0x00)        // ADC1 Gain 1
ADS131A04_WriteReg(0x14, 0x00)        // ADC1 Gain 1
ADS131A04_WriteReg(0x0f, 0x0f)
ADS131A04_Wakeup()
ADS131A04_Lock()

All commands answer correctly.

When the ADS is start and I shift out the 15 bytes (1x Status + 4x ADC results  ) the first two bytes are 0x22 0x20 . Why ?

The ADC results look okay.

Thank you for your help

  • 0
    TI__Mastermind 46055 points

    Hi Roy,

    Are you sending "NULL" command to the ADC? if yes, the first 2 bytes should show STAT_1 register (02h register address + current register value of 0x20). The 0x2220 you received indicates one fault (F_SPI fault = 1b), you can read STAT_S register (address 05h) to see what caused this fault. If you can send me a timing plot for SCLK, DIN, DOUT and /CS, it will be very helpful to address the issue, thanks.

    Best regards,

    Dale

  • 0 in reply to Dale Li
    Intellectual 405 points

    Yes , I send NULL .

    I make a timing via a excel file , so you can zoom in the lines : https://www.dropbox.com/t/QqXrb4tdC32WDCuD

    Lines up -> down :

    READY

    /CS

    SCLK

    MOSI ( DIN ADS)

    MISO (DOUT ADS)

    STAT_S give me 0x01

  • 0 in reply to Roy Wengler
    TI__Mastermind 46055 points

    Hi Roy,

    Thank you for providing it to me. It seems like you got 0x0222 data in the first word, not 0x2220, please confirm. Can you please read STAT_S register (address 05h) and let me know the value? Also, can you please let me know how many SCLKs you send to the ADC in one frame which is highlighted in red below? It's hard for me to check in the excel file. 

    I really suspect you are facing the same issue as the datasheet describes in the section 9.5.2.1.5. The data are not completely shifted out when new data re ready, so the F_DRDY bit in the STAT_1 register is set to high which indicates that the DOUT output shift register is not updated with the new conversion result, this is really what you got on F_DRDY bit (This bit is set if data shifted out from the previous result are not complete by the time new ADC data are ready.)

    Best regards,

    Dale

  • 0 in reply to Dale Li
    Intellectual 405 points

    Hi Dale,

    STAT_S give me a 0x01 and I get 0x2220 :

    0 0 1 0 0 0 1 0  0 0 1 0 0 0 0 0  = 0x2220

    Here my Settings:

    ADC clock : 20MHz

    SPI clock : 30MHz

    ADC conversion interval : 100µs

    SPI communication need ~ 6µs

    Best regards

    Roy

  • 0 in reply to Roy Wengler
    TI__Mastermind 46055 points

    Hi Roy,

    Thank you for providing more information.

    As you mentioned, the bit 0 of  the STAT_S register (F_FRAME bit) is set, this indicates that "Not enough SCLKs are sent per frame" to the ADC. I checked your register initialization again. When you initialize the registers, you write 0x32 to the D_SYS_CFG register (address=0x0C), this command enables "Fixed word size" and selects "Fixed six words per data frame for the ADS131A04. Since you have chosen to use a word size of 24 bits by shorting M1 to GND, so you should have total 6*24 = 144 bits in a single frame.

    I was able to zoom-in and check your timing in your excel file. You are sending 5 words which have 5*24 = 120 SCLKs to the ADC as shown in the following graph, so this is the root reason why F_FRAME bit is set in the STAT_S register and the F_SPI is set in STAT_1 register.

    Please send enough SCLKs to the ADC and check again. Let me know the result, thanks.

    Note that the F_FRAME bit can be cleared when you read the STAT_S status register. However, you need 3 frames to accomplish this.

    Best regards,

    Dale

  • 0 in reply to Dale Li
    Intellectual 405 points

    Hi Dale,

    thanks for your daily help.

    You are right, with the 6*24 SCLKs.

    I change it to 6x24 Bits , but I get the same result.

    I also changed it to 30x24 Bits, -> the same.

    I changed the D_SYS_CFG register to its reset default  and read 5*24 Bits -> the same.

    Every time I get the 0x2220 ...

    But since the result of the ADC channels still fits, I leave it that way now.

    Thank you

    Roy

  • 0 in reply to Roy Wengler
    TI__Mastermind 46055 points

    Hi Roy,

    Thank you for letting me know.  I found a few threads that may be able to help:

    I will try to find an EVM board and check it according to your configuration. Thank you.

    Best regards,

    Dale