This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
I am using ADS131 in my data acquisition device. ADC works fine, I am pretty happy with it. After initial debugging I have noticed that in the status word after transmission bit 6 is high. According to the datasheet it means that there is an SPI related problem. After investigation of the STAT_S (0x05) register content I saw that only bit 0 is set. It corresponds to message: Not enough SCLKs are sent per frame.
Some details about my implementation: no hamming code, 24 bit word, asynchronous slave mode. Fixed word size is disabled, no CRC (checked in the 0x0C register). I use MCU with SPI to read the measurements. ADS131 provides me with 4 24 bit measurements and 24 bit status word (padded with zeros). I use 8 word long FIFO on MCU side, with FIFO word is 2 bytes long. This means that after DRDY provides ready signal MCU inserts enable, CLK signals for 128 (8*16) clock cycles (I write zeros to MOSI in order to keep SPI active). ADC needs 5*24=120 clock cycles to send all bytes. If I didn't miss anything it should be enough to read all data.
As I have mentioned measurements look good I have no problem. I am just wondering why ADS131 sets this alert. I attach below scope screenshot, it can be seen that truly enable signal (dark blue) and clock (light blue) are active longer than ADC is sending data (MISO is violet). Sampling frequency is 20.830kHz.
BTW, ADS131 doesn't have programmable offset calibration, yes?
Thanks in advance.
Hi Alex,
Thank you for the response. In my original post the dark blue signal is CS line. It gets high as soon as transmission is finished. So yes, it is toggled then and minimum high time according to the documentation is tw(CSH) 20ns, is much longer high than this.
Hello Lukasz,
Thanks for your patience while we look into this.
As you mentioned, bit 0 of the STAT_S register is set when not enough SCLKs are sent in the frame. Given that you are actually sending 8 extra SCLKS, I do not expect this bit to be high. I can double-check with the digital designer how this bit should behave for extra SCLKs in a frame.
When you read the STAT_S register, the F_FRAME bit should be cleared. Have you tried reading the STAT_S register in back-to-back frames to confirm that this bit is cleared? You will need 3 frames to accomplish this, similar to what is shown in Figure 75.
Best Regards,