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Hello! I am using MSP432 to communicate with ADS131A04 ADC using 32 bit words, at 1MHz SPI clock.
The problem is that after I enable the ADC channels (in 0x0F register) I get STAT1 = 0x2220 (indicating a fault with SPI), and when reading STAT_S I get 0x2501 which is F_FRAME fault. I've tried clearing the bit by reading STAT_S many times, but it will not clear. The bit will clear only after if I disable the ADC channels and read STAT_S.
I mention that I am using the same read/write functions, so there should not be any issues related to insufficient SCLKs. Also, even when F_FRAME is set, I am able to successfully read/write the ADC's registers. I've attached the logic analyzer capture so you can have a look (you need Saleae Logic software to open it; it can be downloaded for free).
Is this normal behavior? If not, why is F_FRAME set only when the ADC channels are enabled?
I've done the following test: read ADC_ENA register, write ADC_ENA register to enable channels, read STAT_S register. I've attached the logic analyzer capture.
After enabling the channels, I've tried reading 4, 5, 6 (current case), 8, 10 bytes, but it always return 0x2220 (F_FRAME fault). According to Figure 51 in the datasheet, it should work with 5 bytes (I'm using dynamic frame size with CRC disabled).
Does anybody know how to properly communicate with this ADC?
Hello Cristian,
Tom is currently on vacation, so I will help you in the meantime.
I believe you are confusing the terms "byte" and "word." Of course, a byte consists of 8 bits. However, you have chosen to use a word size of 32 bits (M1 = 1), which is equal to 4 bytes. Every command, channel data, or CRC output will use the same word length of 4 bytes.
Let's assume you have all 4 ADCs enabled as well as CRC. You will see 6 words in each frame on DOUT as shown in Figure 51. These words correspond to Command Status, Channel 1, Channel 2, Channel 3, Channel 4, and the CRC. Therefore, a single frame will consist of 192 bits or 24 bytes. You will need to keep /CS low during the entire frame to read the data properly.
In Dynamic Frame Size (D_SYS_CFG[1] = 0), channel data and CRC can be removed from the frame if they are disabled. This is shown in Figure 50 and 51 b) and d).
Best Regards,
Yes, you are right. I used 20 bytes for reading sample values (I have disabled CRC), but I forgot that I have to read 20 bytes immediately after enabling the ADC channels. It works fine now. Thank you!