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ADS131A04: Why does F_FRAME fault appear after enabling ADC channels?

Cristian Monea
Expert 1795 points
Part Number: ADS131A04

Hello! I am using MSP432 to communicate with ADS131A04 ADC using 32 bit words, at 1MHz SPI clock.

The problem is that after I enable the ADC channels (in 0x0F register) I get STAT1 = 0x2220 (indicating a fault with SPI), and when reading STAT_S I get 0x2501 which is F_FRAME fault. I've tried clearing the bit by reading STAT_S many times, but it will not clear. The bit will clear only after if I disable the ADC channels and read STAT_S.

I mention that I am using the same read/write functions, so there should not be any issues related to insufficient SCLKs. Also, even when F_FRAME is set, I am able to successfully read/write the ADC's registers. I've attached the logic analyzer capture so you can have a look (you need Saleae Logic software to open it; it can be downloaded for free).


Is this normal behavior? If not, why is F_FRAME set only when the ADC channels are enabled?

8 MHz, 80 M Samples.zip

  • 0
    TI__Guru**** 180941 points
    Hi Christian,

    How is the M1 pin configured on your ADS131A04 device? What are the register contents of the D_SYS_CFG register? In your screen capture, I suspect the 'SPI-ENABLE' line is connected to the Chip Select pin of the ADS131A04, is that right? If you review section 9.5, a data frame consists of multiple data words which are 'framed' by chip select and it looks like you are taking /CS high between each data word. Can you hold /CS low through the entire data frame transmission and let us know if that clears the F_FRAME error?
  • 0 in reply to Tom Hendrick
    Expert 1795 points
    Hello Tom,

    M1 = 1, so I use 32 bit words.

    D_SYS_CFG = 0x3C (default value).
    I see in D_SYS_CFG that FIXED = 0 meaning "Device words per data frame depends on whether the CRC and ADCs are enabled". This somewhat explains why the behavior appears only when ADCs are enabled, however it should not affect me, because CRC is disabled. Do I need to write 5 bytes after enabling the ADCs when checking the register value after writing it?

    The ADC CS (pin 23) is connected to the MSP432 CS pin.

    Currently, every data frame is framed by CS (i.e., take CS low, transmit 4 bytes, take CS high). In this case, shouldn't the error appear earlier and not only after I enable the ADCs?

    Are you suggesting to take CS low, transmit 8 bytes and then take CS high?
  • 0 in reply to Cristian Monea
    TI__Guru**** 180941 points
    Hi Christian,

    Continue reading down through section 9.5 and take a look at figure 51, when CRC is enabled, there is one additional word to the data frame. You still have to account for the enabled ADC channels though.
  • 0 in reply to Tom Hendrick
    Expert 1795 points
    I'm sorry, but I do not understand. In my case, CRC is disabled. I've tried writing and reading with 5 or 6 bytes, by I still get frame fault. What am I misunderstanding?
  • 0 in reply to Tom Hendrick
    Expert 1795 points

    I've done the following test: read ADC_ENA register, write ADC_ENA register to enable channels, read STAT_S register. I've attached the logic analyzer capture.

    After enabling the channels, I've tried reading 4, 5, 6 (current case), 8, 10 bytes, but it always return 0x2220 (F_FRAME fault). According to Figure 51 in the datasheet, it should work with 5 bytes (I'm using dynamic frame size with CRC disabled).

    Does anybody know how to properly communicate with this ADC?

    8 MHz, 160 M Samples.zip

  • 0 in reply to Cristian Monea
    TI__Guru 66316 points

    Hello Cristian,

    Tom is currently on vacation, so I will help you in the meantime.

    I believe you are confusing the terms "byte" and "word." Of course, a byte consists of 8 bits. However, you have chosen to use a word size of 32 bits (M1 = 1), which is equal to 4 bytes. Every command, channel data, or CRC output will use the same word length of 4 bytes.

    Let's assume you have all 4 ADCs enabled as well as CRC. You will see 6 words in each frame on DOUT as shown in Figure 51. These words correspond to Command Status, Channel 1, Channel 2, Channel 3, Channel 4, and the CRC. Therefore, a single frame will consist of 192 bits or 24 bytes. You will need to keep /CS low during the entire frame to read the data properly.

    In Dynamic Frame Size (D_SYS_CFG[1] = 0), channel data and CRC can be removed from the frame if they are disabled. This is shown in Figure 50 and 51 b) and d).

    Best Regards,

  • 0 in reply to Ryan Andrews
    Expert 1795 points

    Yes, you are right. I used 20 bytes for reading sample values (I have disabled CRC), but I forgot that I have to read 20 bytes immediately after enabling the ADC channels. It works fine now. Thank you!