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ADS124S08: DRDY and DOUT/DRDY not going low

Prakash B B
Prodigy 160 points
Part Number: ADS124S08
Other Parts Discussed in Thread: ADS1256

Hi,

I am programming and reading from ADS124S08 ADC using Verilog. It is configured as STATUS = 8'h00, PGA= 8'hEF, DRATE= 8'h5B, REF= 8'h10, MUX = 8'h01, SCLK = 1 MHz, CLK = 4 MHz. The way I programmed is:

After power-on:

1.  CS and START/SYNC driven to low wait for 2 CLK

2. Reset ADC and wait for 4096 CLK

3. Set STATUS and wait for 1 CLK

4. Set PGA and wait for 1 CLK

5. Set DRATE and wait for 1 CLK

6. Set REF and wait for 1 CLK

7. Set MUX and wait for 1 CLK

8. Send START COMMAND (also sometimes I connected START/SYNC to HIGH and no COMMAND used) and wait for 4 CLK

9. Self calibrate (first time only)

10. Wait for DRDY to go low

11. Read data by sending 24 SCLK (direct read. Even I tried with READ COMMAND)

12. Repeat 7, 10 and 11.

By doing this I didn't find DRDY going low. I am stuck at step 10. I am doing it correctly or am I missing any steps?

Thanks

  • 0
    TI__Guru 52336 points

    Hi Prakash B B,

    When you power up the ADC and then bring the START pin high, you should see DRDY pulsing at approximately the inverse of the default data rate (which is 20 SPS, or ~50 ms). This happens without writing any registers, taking CS high/low, etc. Therefore, this is an easy test to make sure that your ADC is functioning. If this does not occur, then you most likely have an issue with the power supplies or the clock

    I would also encourage you to read back the register data you send to make sure it was received by the ADC correctly

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    How are you? Wishing you a very Happy New Year - 2023.

    I did by bringing START pin high after power-up. DRDY is pulsing no doubt in it, but the rate is not at 20 SPS. It is occasionally appearing on the CRO. Unable to capture the period of it.

    Another interesting thing is, when I skipped the RESET and Self Calibration steps, the DRDY is pulsing at 1.5kHz for the settings I mentioned previously. Would you let me know how is it possible? Why isn't it pulsing at default rate after power-up?

    Thanks

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    I am doing well, thanks for asking. And a Happy New Year to you as well!

    If you are powering up the ADC, then pulling START high, and doing nothing else, you should see DRDY toggling at the default data rate on the ADS124S08. If you do not see DRDY toggling, or it is not toggling consistently, then you must have a power supply issue, a clocking issue, or the device has somehow been damaged. It might also be possible that your controller is trying to drive the DRDY pin, causing contention issues. Assuming the device has not been damaged:

    Have you checked to make sure your power supplies are stable and not drooping?

    If you are using an external clock, is this a clean signal feeding into the ADC? If you are using the internal clock, is the CLK pin grounded?

    You might try using an external power supply and disconnect the DRDY pin from the controller to be absolutely sure there are not issues with these connections.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    Thanks for the wishes.

    I checked with the power supplies and found stable.

    The clock is external and from crystal. It seems to be pretty clean.

    It is bit difficult to connect external supply to check the DRDY pin behavior. Let me see the possible way.

    When after programming registers why did DRDY start pulsing at regular intervals but not before?

    Another question:

    Do I need to program registers, START and STOP commands for mux mode every time whenever I switch between differential inputs in continuous mode?

    Thanks

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    What is the part number for the clock you are using?

    Can you try grounding the CLK pin so the ADC uses the internal oscillator? And also try with external supplies? This is the simplest configuration that should allow you to see DRDY toggling at the default data rate (after making sure START is pulled high). Again, you should not send any commands or toggle any other pins to make this work (other than keeping RESET high of course)

    Prakash B B said:
    When after programming registers why did DRDY start pulsing at regular intervals but not before?

    I'm not sure what to make of this. According to your register settings you are setting the DR bits in the DATARATE register to 8'hB, which should select the 1kSPS data rate. However, you said the data rate was actually 1.5kSPS when you measured it, which isn't possible. Even running the ADC at the maximum CLK frequency of 4.5MHz would only increase the output data rate to ~1.1kSPS. I assumed this was just unstable behavior because there are issues elsewhere with the system

    Prakash B B said:
    Do I need to program registers, START and STOP commands for mux mode every time whenever I switch between differential inputs in continuous mode?

    No, you do not need to send the START and STOP commands every time. Writing to the INPMUX register automatically restarts the conversion process. See the WREG section (9.5.3.12) for more information on which register writes cause the conversion process to restart

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    H Bryan,

    I tried grounding the ADC CLK pin to use internal oscillator. When I pulled START High, DRDY was pulsing at default rate (20 SPS, 50 ms). I feel something else is the reason. Need to be checked.

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    Thanks for providing additional information. It appears there is a problem with your clocking circuit. You might want to check the rest of your system using the internal oscillator so you know it behaves as desired. Then you can try to diagnose the clocking issue.

    Or, why not just us the internal oscillator on the ADS124S08 then?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    I don't want to miss any data. So, external clock I am using it. Also, state transition happens w.r.t. this clock which helps me to keep track of it.

    Do think there will be cross between channels when multiplexed? How do I resolve this?

    Is there any possibility that AIN0 & AIN1 differentially work and AIN2 & AIN3 do not?

    Regards

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    The reason why I asked is:

    First image noise free bits are (13 to 14) where as other 2 images are not.

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    Prakash B B said:
    I don't want to miss any data. So, external clock I am using it. Also, state transition happens w.r.t. this clock which helps me to keep track of it.

    Why would you miss data using the internal clock? Data output is triggered on and governed by SCLK, which has nothing to do with the internal clock frequency used by the ADC. Perhaps there is a misunderstanding of how this ADC operates

    Regarding your other questions: I don't think there is a possibility that AIN0 & AIN1 works and AIN2 & AIN3 does not, unless the absolute maximum ratings were violated. What you are describing sounds like a settling issue, not crosstalk. In other words, the input signal to the ADC is not settled when you are sampling it, so you get a "noisy" signal. You can try slowing down the output data rate to see if the situation improves. You can also try increasing the programmable delay (DELAY bits in the PGA register 0x03). This feature delays the start of conversion to allow for any external analog circuits to settle. This is usually due to anti-aliasing filter components (resistors and caps) or if there is some switched biasing feature in your application e.g. current or voltage excitation that switches from one sensor to another

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    No no. I am aware that data output is triggered on and governed by SCLK. The intent is also that, if I wish, I can change the ADC frequency too.

    The snaps shared are for shorted inputs. When I configured as differential with AIN0 & AIN1 and inputs shorted I found 13/14 noise free bits (NFB). But when repeated for AIN2 & AIN3 I couldn't. And also when repeated for AIN4 & ANI5 I couldn't.

    I tried delaying as well as changing the DRATE, but no change in second & third differential inputs.

    Also, I observed that DRDY pin is going HIGH on first falling edge of SCLK instead rising edge of SCLK as shown below:

    What do you think would be the reason?

    Is there anything to be taken care while multiplexing or AIN2 & AIN3 differential inputs?

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    So you are using an external clock in case you need to adjust the output data rates? The ADS124S08 already offers 14 different output data rates, that is not sufficient? I only ask because it seems like using an external clock is causing significant issues in your system, and I don't see any real benefit to using an external clock. You might want to reconsider this functionality in your system

    Regarding the noise: I'm not sure I understand what you are showing in the three images from your post yesterday. You said the first image shows that the noise free bits are 13-14, while the other two images are not. How are you drawing this conclusion? Just by seeing that bits 23:11 in the data are not changing? Or are you calculating this? I ask because the other two images also look like the same number of bits are not changing, so I don't understand how you are concluding that one is working and the other two are not

    Section 8 in the ADS124S08 datasheet describes how the noise measurements are made. I would perform the same tests with your system so you can measure the noise under the same conditions. Then calculate the RMS noise (not effective resolution or noise free bits) and compare your result to what is shown in the datasheet. I'm not sure the method you are using right now is very useful.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    Not exactly. Yea, may be if required. But mainly I can keep phase relationship with SCLK which helps me in timing issues. DRATEs are sufficient, no doubt in it. I don't think so the external clock will cause any issue. I used external clock in ADS1256 and found working good. And as I said SCLK related timing issues were better.

    Yes. I am looking at bits 23:11 which indicate NFB. Not any calculation. In other two images in between even the bits 23:11 are toggling indicating that either there is a cross talk and something else. Need a check on it.

    I had referred the Section 8 for checking the ENOB and NFB but not the calculation. The way I am observing should match the Table values for these bits. And it maps too.

    I tried logging-in last day but couldn't. Don't know why.

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    The data in the images shows that the signal is swinging from a small positive voltage to a small negative voltage. This might be warranted given that the input signal is very small (~0V) and the gain is very high (128, at least according to the settings you supplied in your original post).

    I would follow the instructions in Section 8 for how the noise measurements are taken, then actually take the data and perform the calculations (standard deviation, etc.). I would also plot the data to see what it looks like in the time domain. If it looks Gaussian, then you are getting what you should expect. If it's not Gaussian, then you have some external noise source that is interacting with the ADC. With the ADS1256, it was the clocking circuit, so this is where I would start troubleshooting, especially since you've already had issues with the clock in this circuit

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    When I say NFB then the respective number of bits should not toggle for shorted input or connected a load without varying it. Am I right? If so, then the way I calculate NFB should suffice. Right?

    I had used external clock (from FPGA) generated with frequency 4.0886 MHz. When I multiplexed the all inputs differentially and shorted them except AIN2 & AIN3 where I connected the load cell, I got the results as shown below: (SPS = 800, delay = 24, START and STOP commands are used)

    Now DRDY is pulsing at ~655 Hz. Is that the rate correct?

    The use of START & STOP commands with external clock has resolved the issue I think. When used these commands and an internal clock still there was issue. I didn't understand the reason. It may be SCLK phasing. Is that what you also think or something else?

    Thanks

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    I am not sure what "Delay = 24" means, since this is not a valid register setting in the DELAY bits in the PGA register. But note that the programmable delay only occurs once after taking START high or sending the START command. If you are sampling continuously e.g. sending the START command and no STOP command, you should get data out at approximately 1/ODR, or 1/800 = 1.25 ms in your case. This is true for all conversions but the first one, where filter setting and the delay time must be accounted for.

    There shouldn't be any issue using the START/ STOP commands with an internal versus external clock. I am not sure what could cause this issue, it could be many different factors (noise issues, layout issues, firmware bug, communication issues, etc.). If you want to resolve this issue you might start by looking at the communication timing for all signals when you are writing to and reading from the ADC

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    The delay is related to DELAY bits in the PGA setting. It is set as 25*tmod (not 24). But, when I use START and STOP commands then the rate will reduce right?

    I am also unaware on it. The timings are checked for read/write and are well w.r.t. datasheet. Need to know what else would be the cause.

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    If you are using the low-latency filter at a data rate of 800 SPS, the first conversion takes 360 tMOD periods (see Table 13). Then you add another 25 tMOD periods for the programmable delay, which is a total of 385 tMOD periods. For the ADS124S08, tMOD = 16 / fCLK, which in your case is 16 / 4.0886 MHz = 3.91 us. Then, 385 tMODs * 3.91 us = 1506 us, which is an equivalent sampling rate of 664 Hz. So yes you have the correct data rate assuming you are starting a new conversion each time.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    Thanks for the information.

    I am unable to find any issues related to timing as such. Need to know the source of problem.

    Just wanted to know if this is the right platform regarding the current excitation:

    If I am using AIN0 & AIN1 as the differential inputs for example, and are connected to a load cell, then can I send excitation current through the same input lines to transducer (load cell) as excitation source while it is being used as input? Means, can the load cell receive excitation from the these inputs?

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    It is always helpful to see what you are trying to do, as opposed to explaining it in words.

    Can you draw a quick picture of what you want to do with the load cell and the excitation current so I can see how you want to set up the circuit? This will make it easier to tell you if what you are doing is correct

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    For me it is difficult to reproduce in picture, since I am not involved in it. I am FPGA guy. But have an idea. It is:

    Since we are using 4 I/O lines for load cells, 2 for differential signal given to ADC in differential configuration and other 2 are used for excitation to the load. This excitation is voltage based. When ADC is supplying a current upto 3 mA for excitation, is it possible to use this current for converting voltage based to current based excitation?

    If so, can I use the same lines which are connected to differential channel inputs of ADC?

    Hope I am clear now.

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    Should you have someone else ask these questions then, if there are others working on the hardware design? Most of the questions asked thus far have been hardware related, so it would make sense to speak with the person responsible for those decisions.

    Typically the input channels have anti-aliasing filters, which are comprised of a resistor and a capacitor. Since the resistor is in series between the sensor and the ADC, pushing current out of the same pin that is being measured will also push current through the filter resistor, causing a large voltage drop. This voltage drop will be measured by the ADC as part of the load cell output, resulting in a large error. So no, I would not recommend using the same analog input to measure the load cell and for the IDAC output

    If what I am describing is not how you intended to architect your circuit, please send me a picture (or have someone else do so)

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    I will check on this and get back. Since it's my idea of reducing the number of pins, I need to speak with the hardware person. If anything I will inform you.

    This information should be good enough for my intension. Let me re-think on the same.

    I will check on the picture with concerned person.

    Regards

  • 0 in reply to Prakash B B
    TI__Guru 52336 points

    Hi Prakash B B,

    Understood, let us know if you have additional questions. If they are not related to this thread, please start a new one and we will support you there

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 160 points

    Hi Bryan,

    Thanks for the support. I will definitely ping you if any.

    Regards