ADS124S08: DRDY and DOUT/DRDY not going low

Hi Prakash B B,

When you power up the ADC and then bring the START pin high, you should see DRDY pulsing at approximately the inverse of the default data rate (which is 20 SPS, or ~50 ms). This happens without writing any registers, taking CS high/low, etc. Therefore, this is an easy test to make sure that your ADC is functioning. If this does not occur, then you most likely have an issue with the power supplies or the clock

I would also encourage you to read back the register data you send to make sure it was received by the ADC correctly

-Bryan

Hi Prakash B B,

What is the part number for the clock you are using?

Can you try grounding the CLK pin so the ADC uses the internal oscillator? And also try with external supplies? This is the simplest configuration that should allow you to see DRDY toggling at the default data rate (after making sure START is pulled high). Again, you should not send any commands or toggle any other pins to make this work (other than keeping RESET high of course)

Prakash B B said:

When after programming registers why did DRDY start pulsing at regular intervals but not before?

I'm not sure what to make of this. According to your register settings you are setting the DR bits in the DATARATE register to 8'hB, which should select the 1kSPS data rate. However, you said the data rate was actually 1.5kSPS when you measured it, which isn't possible. Even running the ADC at the maximum CLK frequency of 4.5MHz would only increase the output data rate to ~1.1kSPS. I assumed this was just unstable behavior because there are issues elsewhere with the system

Prakash B B said:

Do I need to program registers, START and STOP commands for mux mode every time whenever I switch between differential inputs in continuous mode?

No, you do not need to send the START and STOP commands every time. Writing to the INPMUX register automatically restarts the conversion process. See the WREG section (9.5.3.12) for more information on which register writes cause the conversion process to restart

-Bryan

Hi Prakash B B,

Thanks for providing additional information. It appears there is a problem with your clocking circuit. You might want to check the rest of your system using the internal oscillator so you know it behaves as desired. Then you can try to diagnose the clocking issue.

Or, why not just us the internal oscillator on the ADS124S08 then?

-Bryan

Hi Prakash B B,

Prakash B B said:

I don't want to miss any data. So, external clock I am using it. Also, state transition happens w.r.t. this clock which helps me to keep track of it.

Why would you miss data using the internal clock? Data output is triggered on and governed by SCLK, which has nothing to do with the internal clock frequency used by the ADC. Perhaps there is a misunderstanding of how this ADC operates

Regarding your other questions: I don't think there is a possibility that AIN0 & AIN1 works and AIN2 & AIN3 does not, unless the absolute maximum ratings were violated. What you are describing sounds like a settling issue, not crosstalk. In other words, the input signal to the ADC is not settled when you are sampling it, so you get a "noisy" signal. You can try slowing down the output data rate to see if the situation improves. You can also try increasing the programmable delay (DELAY bits in the PGA register 0x03). This feature delays the start of conversion to allow for any external analog circuits to settle. This is usually due to anti-aliasing filter components (resistors and caps) or if there is some switched biasing feature in your application e.g. current or voltage excitation that switches from one sensor to another

-Bryan

Hi Prakash B B,

So you are using an external clock in case you need to adjust the output data rates? The ADS124S08 already offers 14 different output data rates, that is not sufficient? I only ask because it seems like using an external clock is causing significant issues in your system, and I don't see any real benefit to using an external clock. You might want to reconsider this functionality in your system

Regarding the noise: I'm not sure I understand what you are showing in the three images from your post yesterday. You said the first image shows that the noise free bits are 13-14, while the other two images are not. How are you drawing this conclusion? Just by seeing that bits 23:11 in the data are not changing? Or are you calculating this? I ask because the other two images also look like the same number of bits are not changing, so I don't understand how you are concluding that one is working and the other two are not

Section 8 in the ADS124S08 datasheet describes how the noise measurements are made. I would perform the same tests with your system so you can measure the noise under the same conditions. Then calculate the RMS noise (not effective resolution or noise free bits) and compare your result to what is shown in the datasheet. I'm not sure the method you are using right now is very useful.

-Bryan

Hi Prakash B B,

The data in the images shows that the signal is swinging from a small positive voltage to a small negative voltage. This might be warranted given that the input signal is very small (~0V) and the gain is very high (128, at least according to the settings you supplied in your original post).

I would follow the instructions in Section 8 for how the noise measurements are taken, then actually take the data and perform the calculations (standard deviation, etc.). I would also plot the data to see what it looks like in the time domain. If it looks Gaussian, then you are getting what you should expect. If it's not Gaussian, then you have some external noise source that is interacting with the ADC. With the ADS1256, it was the clocking circuit, so this is where I would start troubleshooting, especially since you've already had issues with the clock in this circuit

-Bryan

Hi Prakash B B,

I am not sure what "Delay = 24" means, since this is not a valid register setting in the DELAY bits in the PGA register. But note that the programmable delay only occurs once after taking START high or sending the START command. If you are sampling continuously e.g. sending the START command and no STOP command, you should get data out at approximately 1/ODR, or 1/800 = 1.25 ms in your case. This is true for all conversions but the first one, where filter setting and the delay time must be accounted for.

There shouldn't be any issue using the START/ STOP commands with an internal versus external clock. I am not sure what could cause this issue, it could be many different factors (noise issues, layout issues, firmware bug, communication issues, etc.). If you want to resolve this issue you might start by looking at the communication timing for all signals when you are writing to and reading from the ADC

-Bryan

Hi Prakash B B,

If you are using the low-latency filter at a data rate of 800 SPS, the first conversion takes 360 tMOD periods (see Table 13). Then you add another 25 tMOD periods for the programmable delay, which is a total of 385 tMOD periods. For the ADS124S08, tMOD = 16 / fCLK, which in your case is 16 / 4.0886 MHz = 3.91 us. Then, 385 tMODs * 3.91 us = 1506 us, which is an equivalent sampling rate of 664 Hz. So yes you have the correct data rate assuming you are starting a new conversion each time.

-Bryan

Hi Prakash B B,

Should you have someone else ask these questions then, if there are others working on the hardware design? Most of the questions asked thus far have been hardware related, so it would make sense to speak with the person responsible for those decisions.

Typically the input channels have anti-aliasing filters, which are comprised of a resistor and a capacitor. Since the resistor is in series between the sensor and the ADC, pushing current out of the same pin that is being measured will also push current through the filter resistor, causing a large voltage drop. This voltage drop will be measured by the ADC as part of the load cell output, resulting in a large error. So no, I would not recommend using the same analog input to measure the load cell and for the IDAC output

If what I am describing is not how you intended to architect your circuit, please send me a picture (or have someone else do so)

-Bryan