Other Parts Discussed in Thread: TX7332,
Hello E2E Experts,
Good day.
As a continuation of the previous E2E inquiry, below are our concerns: TX7332EVM: Needs Urgent Suggestion - Data converters forum - Data converters - TI E2E support forums
(1) How to trigger externally the tx7332 board for data acquisition process, is there any pin used for external triggering in tx7332 pulser board?which pin of tx7332 has to send trigger pulse, which in turn pulsate the tx-rx switch for receiving signal?
(2) During hardware setting, it generates a two cycle pulsed signal at tx pin of tx7332evm by default. how to generate a single pulse instead of two.?
Your answer:
To generate a single cycle, you need to keep the Repeat Count = 0.
Currently, the device is running with a BF_CLK frequency of 200MHz. The frequency can be reduced by writing CLK_DIV = 5. This will reduce the clock to 200/32 = 6.25MHz (160ns). The maximum number of transitions possible is 16, which gives a maximum of 8 transitions per level. The period can be set to an utmost of 30, which gives 32 clocks per period. In this case, we can get a maximum level duration of 32*8*160ns = 40960ns. This will be around 12kHz.
***However, I am getting single cycle pulse signal TR_BF_SYNC pin and pulser output that was fine, but it was in Khz range, which is not helping me. I need in between 100-300hz. I am actually trying to get the TR_BF_SYNC signal in between 100hz-300hz, which i want to use as trigger signal for hardware device. Also the pulser output signal at tx_out pin should come in this range, but its a high voltage signal
***In your second suggestion, u told to get frequency below that u need to
Remove R19 and R20 resistors.
- Connect R17 and R23 resistors.
Feed the clock at J3
Using the above, you should be able to get a low-frequency output., if you feed in a clock of 10MHz and use the maximum CLK_DIV factor of 5.
*** I remove and connect as per ur suggestion and apply an external clock signal of 1MHZ of 2v peak-peak clock signal at J3, but i am not getting any pulsed signal at TR_BF_SYNC pin as well as pulser output, getting a noisy output. Again the problem it is showing, i am giving a 2v peak-peak clock signal, but at the R23 register, i am getting only 100mv amplitude, a signal loss occurs. Again u have told set clock division factor to 5, as I am giving my clock signal externally and have already disconnected my crystal oscillator from the circuit by removing R19 and R20, how this can be set through that tx7332 GUI, will it work?
Regards,
CSC