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Hi Team,
I'm using an ADC with part number: ADS5404IZAY and interfacing the LVDS output with a Xilinx Zyn Ultrascale FPGA. The ADC board we designed has been interfaced with the FPGA board using FMC connector but due to some unknown reasons, I'm getting a periodic distortion with a pattern when the ADC LVDS output data collected is converted to a histogram. I suspect, this distortion is coming somewhere from the ADC within, could you help me troubleshoot this issue? Has something like this been observed before?
I'm attaching a document that contains a few screenshots of the experimental tests that we have ran using a signal generator output as the input to the ADS5404IZAY ADC system channel B (SECTION A: EXPERIMENTS DONE) along with some circuitry related to the ADC. The LVDS data is collected using FPGA.
ADC_ADS5404_debuggin inputs.pdf
Moreover, to give you a context, I'm sharing some major details related to the system here;
1)The differential input PCB tracks of the ADC are 100E impedance controlled. The LVDS output channels are also 100E impedance controlled.
2)ADC operation under 500MSPS.
3)There is an ADC driver with a filter just before the differential input of the ADC channel B. (SECTION C: ADC INPUT DIFFERENTIAL DRIVER CIRCUIT in the document).
4)A clock generator chip with part number: "RC32504A" has been used for providing the high-speed clock signal input to the ADC (SECTION D: ADC CLOCK GENERATOR CIRCUIT in the document))
5)Switching regulators have been used on the board but there's always a high PSRR, low noise LDO before the ADC power supplies.
6)The entire circuit board has a single common ground.
Let me know if there are any additional information required.
Hi Shine,
I setup a ADS5404EVM in the lab and tested it out with 1) an analog input and 2) a test pattern.I also exported the corresponding register writes and provided them here.
You mentioned that "The ADC board we designed has been interfaced with the FPGA board using FMC connector but due to some unknown reasons, I'm getting a periodic distortion" - just to clarify, was this at one point working without distortion?
Additionally, is 40mV and 400mV the input amplitude at the input of the ADC? Or the level of the output of the sig gen?
Regards, Amy
Hi Shine,
Your signal amplitude is very low at 40 mV and 400 mV – my sig gen requires 691 mV, or 9.8 dBm to reach full scale. I replicated what you are seeing on your board by setting this up on our ADS5404EVM in the lab. Due to the very low signal amplitude, I see a similar result.
With an analog input of 10 MHz, the datasheet indicates the ADC will have an SNR of around 60 dB.
Using the equation for SNR [SNR = 6.02N + 1.76] ----> 60 dB = 6.02 N + 1.76 ----> N = 9.8 = ENOB. In an ideal world, a perfect 12-bit ADC would use all 12 bits. However, due to various source of noise, the ENOB is reduced.
The full scale voltage for this part is Vfs = 1.0 Vpp and the LSBrms = Vfs / 2^N ----> ((1/2) / sqrt(2) / 2^(9.8)) = 396.6 uVrms. Using a signal with an amplitude that drives the ADC to a full scale input, the max number of resolution steps are used ----> 691 mVrms / 396.6 uVrms = 1742 steps. With a signal amplitude of 400 mVrms ----> 400 mVrms / 396.6 uVrms = 1008 steps and at 40 mVrms ----> 40 mVrms / 396.6 uVrms = 100.8 steps are used. This is the math behind why the signal appears to have distortion at low amplitudes – the lower the signal input, the less resolution steps are used.
Are you filtering the clock and signal into the ADC? If using a low-quality signal generator (like a function generator), it is expected that you would see poor signal quality and significant distortion.
Regards, Amy
Regards, Amy
Hi Shine,
I setup the ADS5404EVM with a gaussian white noise generator for the analog input, please see attached histogram.
The schematic and clock source look ok to us, just double check that you have followed the recommendations in the datasheet for the clocking part.
I have also attached the register writes that I am using, you can double check these at well.
Regards, Amy
