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ADS131M08: Error due to random Bit tilting (Bit 15 + Bit 23)

Robert Tannhaeuser
Prodigy 20 points
Part Number: ADS131M08

Dear community and support team,

We have a problem with the ADS131M08. In a current batch we noticed an unusual noise in the output signal of some channels. We then examined this very closely and came to the conclusion that bits are flipping on some channels. According to our measurements, it seems that the first bit of a byte seems to randomly topple, i.e. bit 15 and bit 23. We have not yet ruled out that it also affects bit 7, but this seems to be negligible due to the noisefloor.

For example, we have observed that during a measurement, channels CH1 to CH5 run correctly, and at CH0 the output value jumps and bit 15 flips randomly:

From: 1111 1111 1111 1011 0011 0010 0010 1010.

To: 1111 1111 1011 1011 0010 0101 0011

This gives a jump in the output value from -314838 to -282029. We have documented this in image "ADS131_Failure_CH0.png".

In another measurement, bit 23 at CH5 of the same IC flipped as well.

From: 0000 0111 1000 0110 1010 1111

To: 1000 0111 1000 0110 1100 1101

Which means a significant jump in the output value from 493231 to -7895347. We have documented this in image "ADS131_Failure_CH5.png".

Further measurements show that bits are tilting in certain areas. This could also explain why some channels show no bit errors (jump at the output value) while others have them frequently.

For this we made a measurement and swept the input signal from +0.6V to -0.6V. At first glance you can see almost no error, but if you calculate y(n) = y(n)-y(n-1) you can see very clearly that there are areas where bits flip. Here in this case bit 15 is tilted again. We have attached an image that documents that behavior: "ADS131_Failure_Sweep.png".

As additional infomation, we use the internal reference of the ADS131.

What can cause or explain such a tilting of a bit at the beginning of a byte?

Has such an error or a similar error already been noticed and is there an errata available?

So far, we have only one system where this error occurs. But honestly, we don't know yet how many other systems and ADS131 could be affected.

We therefore ask for a lively discussion here and hope for support on this topic.

Best Regards,

Robert

  • 0
    TI__Mastermind 45805 points

    Hi Robert,

    I did not receive such report before. I have some questions and request:

    1. Did you monitor the /DRDY to retrieve the data? I mean, did you read data once when each falling edge of /DRDY was detected? 
    2. Can you please provide more information about the ADC? e.g. data rate, gain, clock or others.
    3. Can you please provide the raw data and also let me know your input signal for each?

    I will take a look at what you can share with me above, then a schematic will be helpful for further check. Thanks.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 20 points

    Hi Dale,

    I would like to answer your questions briefly:

    1. Did you monitor the /DRDY to retrieve the data? I mean, did you read data once when each falling edge of /DRDY was detected?

    Yes, we use the \DRDY signal as an interrupt. We have also looked at it with a logic analyzer. Here we only noticed that the low period fluctuates between 35 us and 45 us. Of course, it may be that we have not yet seen an anomaly in all the data.

    1. Can you please provide more information about the ADC? e.g. data rate, gain, clock or others.

    We have varied the data rate between 250 Sps, 500 Sps and 1 kSps. Gain is 1. The clock is an external XO (SIT1602BI-12-30E-8.192000), with the recommended 8.192 MHz and +/-25 ppm stability.

    1. Can you please provide the raw data and also let me know your input signal for each?

    The input signal on CH0 was an external signal generator (sinusoid) between -0.6 V and 0.6V.  All other Channel where pretty much constant but had bit tilting as well.

    Furthermore, I attached the schematic of the ADC. Unfortunately, I can't provide further schematic data so easily. But since we already have working boards, the error doesn't seem to be necessarily in the schematic.

    Furthermore, today we observed that the output signal of all channels was massively noisy (actually it was completely different and wrong data) when we measured/connected the SPI_SCK line. Every time we got to the SCK line of the SPI with test leads or the logic analyzer, the data was pretty much garbage to say the least.

    ADS131_Eval.pdf

    CH0 at frequency generator, +-0V6 sinusoid, bit toggles in many ranges.xlsx

    Regards,

    Robert

  • 0 in reply to Robert Tannhaeuser
    TI__Mastermind 45805 points

    Hi Robert,

    Thank you for providing more information and the data. You data shows the code jump could be 33xxx which is pretty high. According to your description, it seems that your SCLK (or SPI bus) is very sensitive. is the pcb trace of SCLK or SPI bus between the ADC and the microcontroller long? Does the M08 ADC share the SPI bus with other device?

    Can you please do two tests below and check output code again?

    1. Short the SIGx input on your circuit board to the GND.
    2. Short the ADC's input internally by programming MUX[1:0] to 01b for each channel.

    Regards.

    Dale