DDC114: Test mode operation error

Hi,

May I ask which customer is this? If not allow to disclose in public, I can reach out to you via email.

Is this thread a duplicated thread as this?

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1237026/ddc114-default-value-in-test-mode

?

I will get back to you around 6/15

Hi Yang,

Yes duplicate thread for the same customer. That thread will be closed.

Thank you.

JH

Hi,

Thanks.

May I ask which customer is this before I can support?

If not allow to disclose in public, I can reach out to you via email.

Thanks

Hi,

I sent you the customer information by private message.

Thanks,

JH

Hi Yang,

The customer has fixed the above test mode output issue.

When RANGE is set to 7 and in test mode (with TEST PIN applied as HIGH), the data for each channel is read at around ‘277’ instead of 0.
If one pulse (HIGH -> LOW -> HIGH) is applied to TEST while the CONV pin is maintained at HIGH or LOW, the data value ‘2375’ is read. As shown in the figure below, They think 11pC is applied as shown in the picture below.

1. Are these test procedures and results correct?

2. Is there a way to switch to sleep mode? Is it appropriate to disable all CLKs and apply RESET to LOW?

Thanks,

JH

Hi

I will get back to you around 6/22

According to datasheet page 12, 

If TEST is held high during the entire integration period, the integrators measure a zero value.

To apply packets of charge during Test Mode, simply strobe TEST low then high before the next CONV transition.

Each rising edge of TEST causes approximately 11pC of charge to be transferred to the integrators.

Customer can refer and compare their timing diagram with page 12 -

Don't know what does customer mean by "sleep mode". There is no sleep in datasheet.

Thanks