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TI-JESD204-IP

Gal Davidi
Prodigy 30 points

Other Parts Discussed in Thread: DAC38RF84, TI-JESD204-IP

Hi,

In my design i plan to interface the DAC38RF84 with Kintex 7 FPGA, my Tx IP transmits two buses (I and Q each 16 bit wide), so 2x16.

Questions:

1. will the TI-JESD204-IP be able to support this scheme? do i need to pre-interleave the I and Q data?

2. I have sent a request for this firmware and there is no reply for several days now, how can i obtain this FW?

Thanks :)

  • 0
    TI__Mastermind 18831 points

    Hi Gal,

    Your request for the TI-JESD204-IP was approved and you should receive an email with additional information. 

    The TI IP can be configured to send your custom data to the DAC. In the provided examples you will be able to see how the data is packed and sent to the DAC.

    Regards,

    David Chaparro