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ADC3660: Testing the ADC that is interfaced to Zynq7010 FPGA

Part Number: ADC3660

In my custom board I am using this IC ADC3660 to read the voltage input , calculate the transient values and record in NAND flash.
The ADC is controlled using SPI lines. I my case there was requirement of four ADC channel, so I have two 16bit ADCs.

In the custom board, I need to make sure that ADC is up and running, and also make sure that the values that are processed by the ADC IC is matching with the expected once.

These three things can be ensured by doing the following tests:-
0. Configuring the ADC: Through kernel how this can be achieved?
1.To see the connectivity and working of ADC is correct : XJTAG library for the IC ADC3660
2. To check the correctness of value: Write a simple application / kernel script that reads the adc and shows the corresponding values

I need help these points.
The zeroth point will make sure the sample rate ,.. are taken care of.
The first point will make sure that the ADC connections are appropriate (without firmware)
The second point will make sure that the ADC is responding to SPI and there is no discrepancy (with firmware).

Please provide me any reference with respect to these three points.
If the XJTAG library is available please share that too.

Below I am providing the snap from my schematic.


Thanks,
Sameeksh M Shetty

  • Hi Sameeksh,

    I will check on this and get back to you.

    Thanks, Amy

  • Hey Sameeksh, 

    We currently do not have any libraries written for the ADC3660 in Linux for an embedded system like this. We typically do programming SPI programming via. an FTDI chip and do sample management our capture cards in a Windows environment. 

    I have some additional questions for you. 

    1. What sample rate do you want to the run the ADC at? What kind of signals do you plan to digitize?

    2. What kind of instantaneous bandwidth do you need in your system?

    3. Are you using the ADC in dual channel mode?

    From there I think we can figure out a way to get you a register map for the ADC that you can program into the device using a method of your choosing. 

    Regards, 

    Matt

  • Hi Matthew,

    To answer your questions 

    1. The sampling rate is 10Mhz 

    2. Bandwidth we are targetting is 16 bit per channel.

    3. We are using ADC in dual channel mode. 

    It will be helpful if you can provide any standard C application used for testing or FPGA source code used on EVM boards.

  • Hi Sarfaraz,

    I have attached the required register writes for the configuration you mentioned. Like Matt mentioned, we typically program the device via SPI. 

    Regards, Amy

    ADC3660_regwrites_10M_16b.txt
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    0x7 0x0
    0x8 0x0
    0x9 0x0
    0xd 0x0
    0xe 0x0
    0x11 0x0
    0x13 0x0
    0x14 0x0
    0x15 0x0
    0x16 0x0
    0x19 0x12
    0x1a 0x0
    0x1b 0x88
    0x1e 0x0
    0x20 0x0
    0x21 0xf0
    0x22 0xf
    0x24 0x0
    0x25 0x0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX