ADC3424: Maximum sample rate and output LVDS frequency of ADC3424

In ADC3424 datasheet P.1, ADC3424 device spec is noted as follows,

"12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter"

On the other hand, in ADC3424 datasheet P.5 (Recommended Operating Conditions), it is noted as follows,

"(3) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS."

Do you mean about this note?

Can we get 500MSPS input analog signal sampling with ADC3424?

If we can do it, how do we get the LVDS output signal frequency?

Is it 3GHz? (It mean 2-wire 500MSPS 12bit output signal 500 x 12 / 2 = 3000MHz.)

Thank you.

Yoshinori Kikui