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ADC08100: Valid data timing window

Part Number: ADC08100

Hello, I am planning on interfacing with the ADC08100 with an FPGA. The sampling frequency is 100 MHz and I was analyzing if timing is stable and met.

However, after looking at the values of the datasheet, I am finding very difficult to use this device.

In the specification, it states that, after the rising edge the data is held valid for 4.4 ns, which means that the data can't be read on the falling edge. 

It also states that, after rising edge the data is valid after 8.5 ns (worst case).

For a period of 10ns, does this leave a 1.5 ns window the fpga to read the digital lines? If we include propagation delays this proves to be very difficult to achieve.

  • Hi Ricardo,

    The tod spec is referring to the amount of time after the clock rising edge the data will be ready at the digital output. Once the data is ready then the next rising edge can be used to sample the output data, which will be held valid for around 4.4ns. 

    Regards,

    David Chaparro