This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS805: Input RC design constraints

Part Number: ADS805

Does ADS805E have any restrictions on the RC design of the input end?

Since the minimum hold time is 3.9ns, Is there any conversion formulas for the RC at the input?

Thank you

Tony Liu

  • Hi Yuxi,

    Just to clarify, you are concerned about the RC network on the analog input frontend? For a filter?

    If so, there are no constraints. The RC network, should be set to the application BW needed for the design.

    Regards,

    Rob