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Does ADS805E have any restrictions on the RC design of the input end?
Since the minimum hold time is 3.9ns, Is there any conversion formulas for the RC at the input?
Thank you
Tony Liu
Hi Yuxi,
Just to clarify, you are concerned about the RC network on the analog input frontend? For a filter?
If so, there are no constraints. The RC network, should be set to the application BW needed for the design.
Regards,
Rob