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Original question:

ADS1118: The bit0(reserved) in configuration register

ADS1118: The config register bit0 read back 0

Victoria Qin
Intellectual 2960 points
Part Number: ADS1118


Hi experts,

Good day! My customer is using ADS1118 in BMS. They encounter an issue in testing SPI comm. RD wrote 1 to bit0, but some times read back is 1, some times read back is 0.

According to datasheet, bit0 should always reads back 1. After check with customer, there is no issue on other bits. 

So is there any similar case before? And does it have any influence on SPI communication? How to avoid it?

Let me know your kind comments.

Regards,

Victoria.

  • 0
    TI__Expert 8855 points

    Hello Victoria,

    Bit 0 should always read back as 1. The fact that you are not reading back 1 possibly indicates a communications error. Could you check and ensure that the values of both registers are as expected? And if the registers seem to be reading back as expected could you send an oscilloscope shot of one of the failed SPI transfers?

    Thanks,

    Levi DeVries

  • 0 in reply to Levi DV
    TI__Intellectual 2960 points

    Hi Levi,

    I have checked, customer wrote  0x40EB, but sometimes reads back 0x40EA.So only this bit0 has issue.  

    I noticed the old gen of this device in other posts, it's same as customer's scenario. If customer is using the old gen, I think it will happen. 

    What do you think? 

  • 0 in reply to Victoria Qin
    TI__Expert 8855 points

    Victoria,

    After checking with out experts it seems there is an error when the ADS1118 is read using continuous SCLK speeds greater than 1MHz, where this bit gets corrupted and will read a 0 instead of a 1.

    To prevent this error we recommend ensuring there is at least 16µS between the first bit and the 17th bit in data transfer. Is the SCLK speed faster than 1MHz?

    Thanks,

    Levi DeVries

  • 0 in reply to Levi DV
    TI__Intellectual 2960 points

    Levi,

    Appreciate for your internal check. Customer is using analog SPI and the freq is only 100kHz. Due to there is no issue on other bits and tight RD resource, this issue would be suspended. I will show you clk waveform and registers value once RD refocus on this issue.

    BR,

    Victoria