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TI-JESD204-IP: How to use TI-204C-IP on Vivado block design

Takeo Senshiki
Prodigy 135 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADC12DJ5200RFEVM

Hello.

I would like to integrate TI-204C-IP to Vivado block design (GUI).

however It's my first time handle it, there are so many things that I don't know.

Could you help me?

My Development Tool/Board

  • - Vivado 2020.1
  • - ADC12DJ5200RFEVM
  • - TI-204C-IP 
  • - Kintex Ultrascale (KCU115) FPGA Board

Question 1
　When using the TI-204C-IP, is it necessary to use Ultrascale FPGA Transceivers Wizard ?

Question 2
　When using the TI-204C-IP, is it necessary to use Xilinx's JESD204-PHY IP ?

Question 3
　I would like to know the specifications of the input/output pins that appear when the TI-204C-IP is placed in a Vivado block design (GUI).
　I looked at the user guide(TI204c-IP-Users-Guide.pdf), but it was not clear what to connect to each pin.  I currently referenced is as of the V1.10 2021/5/18.
　

　
Regards, 

Takeo

  • 0
    TI__Intellectual 1720 points

    Hi Takeo-san,

    The TI JESD IP is not architected for use with the Vivado IP integrator/block design methodology. This will be supported in the next release of the IP, which is planned for Jan 2024. For the current version of the IP, the recommendation is to integrate it using RTL instantiation. 

    To answer the question about the PHY, the TI JESD IP includes the FPGA PHY (transceiver), so there is no need to use the Xilinx JESD PHY IP. The transceiver (xci) file is part of the reference designs in the JESD IP archive. The reference designs show an example of how the IP can be used, so it is necessary to use the transceiver wizard to customize the PHY for your final application needs. 

    Regards,

    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 135 points

    Hi Ameet-san,

    Thank you for your prompt response. I’ｍ looking forward to the next release (Jan 2024). Since I am developing FPGAs for the first time, it would be very helpful to be able to use  the block design methodology. Ideally, It would be better if TI-204C-IP would be supported by Vivado 2023.x or later. 

    https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1260281/ti204c-ip-compatibility-with-vivado-2023-1

    Do you know if the next release will support Vivado 2023.x or later?

    And thank you also for your answer about PHY. I am relieved to hear that it is what I expected.

    Regards,

    Takeo