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Original question:

DAC38RF89: Minimum SYSREF+/- and DAC_CLK+/- Input Differential Voltage and Min/Max input common mode voltage?

DAC37J82: SYSREF Vcom and Vidpp level

Piet Du Toit
Intellectual 370 points
Part Number: DAC37J82
Other Parts Discussed in Thread: LMK04828

Hi Ti
I have a question on the Common- and differential mode input level on the DAC37J82

The datasheet states

  • Vcom = 0.5V
  • Vidpp = 400 to 800 mVp2p

The DAC SYSREF termination on the EVM Board is

  • 200 Ohm to ground
  • 100 Ohm series + 100 Ohm parallel (voltage divider)

The IBIS model simulation of this setup provides a 200 mV Diff p2psignal with the P&N level at 850 & 1005 mV,

This violated both the Vcom and minimum input Diff voltage specification of the datasheet.

Questions

  1. What is the minimum Diif input voltage for SYSREF
  2. Is a Vcom of 1V +/- 200 mV acceptable

Should the DC coupled SYSREF termination be changed to more closely match the SYSREF specification in the datasheet?

Please advise

Thanks

Piet

  • 0
    Intellectual 370 points

    See simulation of SYSREF LMK04828 and DAC3884 IBIS files

  • 0
    TI__Mastermind 23920 points

    Hi Piet,

    The LMK04828 output for the DAC SYSREF is LVPECL2000mV, which has a common mode (described as VOD ; output voltage) of 960mV and roughly 2Vpp swing. This rather strange termination configuration on the EVM is to provide the LMK04828 with a termination to ground somewhere near the desired 240ohm per leg (as required by LMK04828 for LVPECL output formats), and then dividing each leg with a 50% voltage divider as you pointed out which shifts the common mode to roughly 480mV with a differential swing near 1Vpp (500mV per leg). This is close enough to the 500mV desired common mode that there will not be any problems and the swing is above 400mV so there is no issue there either. With a 1V common mode, the buffer for the SYSREF pins will likely be saturated to the point where no futher signals in the sysref path will be 'toggled' inside the DAC.

    If possible, you can ac couple sysref and use a pulsed-continuous sysref mode or even continuous sysref and powerdown after devices are up. On the DAC side, you can select different types of SYSREF modes as well, such as "Skip one SYSREF pulse then use all pulses" 

    Regards, Chase 

  • 0 in reply to Chase W
    Intellectual 370 points

    Hi Chase

    I understand the datasheet as follows:

    • Vod is the Differential output voltage
    • The common mode voltage (Vcom) is the difference between Voh and Vol, i.e. Voh - Vol

    For the three LVPECL options, Vcom is:

    • LVPECL (1600) : 1.88 V
    • LVPECL (2000) : 1.73 V
    • LCPECL           : 1.095 V

    The lowest Vcom of the three is LCPECL, which is suggested for DC coupled SYSREF (9.1.9.6 in the datasheet).
    "LCPECL allows for DC coupling SYSREF to low-voltage converters"

    I got the best DC coupled SYSREF (LMK to DAC) IBIS model simulation results with the following configuration

    • LCPECL output on LMK
    • 121 Om termination resistors on LMK output
    • 100 Ohm series + 80 Ohm to grond (voltage divider) 

    This produces an input on the DAC's SYSREF of Vcom = 0.5 V and Vidpp = 533 mV (see image attached)

    Please advise is the above termination of the LMK LCPECL output is acceptable.

    Regards

    Piet

  • 0 in reply to Piet Du Toit
    TI__Mastermind 23920 points

    Hi Piet,

    My apologies, yes, Vcom is correct. I was answering this using my phone last week and got my labels incorrect. Vod is output swing of LVDS. I think the termination is fine but let me move the thread to the clock team which can provide firm yes/no.

    Regards, Chase

  • 0 in reply to Chase W
    TI__Genius 10995 points

    Hello Piet,

    Looking at your simulations, if you are obtaining the desired swing for the DAC then that termination should not affect the LMK. Mainly the output terminations we suggest are for the customer to obtain the desired swings and Vocm they need for their applications, so that should be fine from the LMK perspective.

    From your description, it looks like you described the below figure, is that correct? Again, that should be fine since you are obtaining the desired swing, but I just want to better understand what you did. Thanks!

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Intellectual 370 points

    Hi Andrea

    Correct, this is the configuration for the DC coupled SYSREF output to the DAC.

    Regards

    Piet

  • +1 in reply to Piet Du Toit
    TI__Genius 10995 points

    Hello Piet,

    Then my suggestion above should work for your design.

    Best,

    Andrea