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Original question:

ADS52J90: ADS52J90

ADS52J90: Startup Initialization

Austen Royer
Prodigy 120 points
Part Number: ADS52J90

I have two questions regarding the ADS52J90 startup sequence:

  1. What is the consequence of the startup power rail ramp sequence not being strictly followed? That is, if the 1.2DVDD, 1.8DVDD, and 1.8AVDD all are set to the right voltage, but don't follow the ramp pattern shown in Figure 95 of the datasheet, will the ADC be damaged? Will the ADC not be damaged, but also not function properly unless the power rails are ramped up correctly? Or is the only downside to not following the ramp sequence that the ADC lifetime is reduced?
  2. Are there any other SPI registers that *need* to be written to other than 0x0A to start the ADC into a test pattern generation mode? Currently I am following the startup sequence exactly (with the exception of the power rails) in Figure 95, with the sampling clock turning on, then a 10 ms HW reset pulse, then the SPI initialization, then a 10 ms TX_TRIG pulse, but all that happens is that the DCLK pin toggles while FCLK and DATA pairs are inactive. The registers I write to, in order, are:
    1. 0Ah - Write 3000h to initialize ADC
    2. 02h - set to 4100h to set PAT_MODES[2:0] and PAT_MODES_FCLK[2:0] to 010 -> deskew pattern
    3. 03h - set to all zeroes to select 12 bit mode, disable digital offset and gain compensation
    4. 04h - set to all zeroes to select 12 bit serialization, all LVDS channels sharing same test pattern
    5. 01h - set to all zeroes to disable JESD, enable LVDS, choose 32 channel mode
    6. Is there a specific order to the SPI transactions needed? Des the 0Ah register write need to come after the SPI initialization?
  • 0
    TI__Expert 4701 points

    Hi Austen,

    Austen Royer said:
    What is the consequence of the startup power rail ramp sequence not being strictly followed? That is, if the 1.2DVDD, 1.8DVDD, and 1.8AVDD all are set to the right voltage, but don't follow the ramp pattern shown in Figure 95 of the datasheet, will the ADC be damaged? Will the ADC not be damaged, but also not function properly unless the power rails are ramped up correctly? Or is the only downside to not following the ramp sequence that the ADC lifetime is reduced?

    There is no risk of device getting damaged. Just it will consume higher current. As mentioned in datasheet "If the AVDD_1P8 supply rises before the DVDD_1P2 supply, the AVDD_1P8 supply current is several times higher than the normal operating current until the time the DVDD_1P2 supply reaches the 1.2-V level.". Once supply is up then ADC will function normally after applying hardware reset.

    2: Your test sequence looks fine to me. Registers can be programmed in any order. What observation are you having after setting these registers?

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 120 points

    Hello! Thank you for your response, the startup issue was root caused as a PDN pin being default pulled-up elsewhere in the design, holding the ADC in power down.

    My final question about startup initialization for the ADC is regarding changing the ADC configuration over SPI. I am setting the ADC into test mode to use the test pattern to align my data reception logic. After aligning the data, I want to switch it back into normal operation (PAT_MODES[2:0] = 000). If I follow the procedure from figure 95 to get the ADC into test pattern generation mode, then do another set of SPI transactions to set the ADC into normal operation, do I need to apply a second TX_TRIG pulse after setting it to normal operation? Will that change the data to clock delay?

  • +1 in reply to Austen Royer
    TI__Expert 4701 points

    Hi,

    Just SPI transaction is enough to switch device from test pattern to normal operation. You dont need to apply TX_TRIG.

    Thanks!

    Regards,

    Shabbir