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DAC37J84: DAC37j84 safe condition

Li Yang
Prodigy 100 points
Part Number: DAC37J84

Hi, Support

    Currently we have a FPGA circuit board interfacing with DAC37j84 boards via FMC connector. However the power for FPGA board and power for DAC circuit board side are separated.

My question is that : " Is it safe the FPGA side powered up while the DAC side doing power cycling?? Will possible the Tx line from FPGA side causing any damage to the DAC end?? "

thanks

Li

  • 0
    TI__Guru 69884 points

    Hello Mr. Li,

    The FPGA Serdes transmitter and the DAC37J84 RX[0:7] SerDes receivers are typically AC coupled. Therefore, the common mode voltage when FPGA is first powered up and then the DAC37J84 are isolated by the AC coupling capacitor.

    Please ensure that FPGA SerDes transmitter is *not* having any AC swing during DAC side power cycling. For example, when the FPGA is powered up firstly, please have the SerDes transmitter in a tr-state mode where the SerDes transmitter is not having any swing AC bit wise. You can then power up the DAC37J84. When DAC37J84 is completely powered up, you can then enable the FPGA SerDes transmitter from tri-state.

    Basically, we want to make sure the AC swing is not exceeding the absolute maximum specification, when VDDT is 0V

    -Kang

  • 0 in reply to Kang Hsia
    TI__Guru 69884 points

    Mr. Li,

    I have also received some inquiry from Ms. Obinna. I will need to think about the JESD204 stability and get back to you.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 100 points

    Thank you, Kang..

    What about the situation that when the FPGA still communicating with DAC, the DAC side circuit powered down?? Will the FPGA JESD tx line still trying to send data out?? or when link is down, the tx line will be turned to a tri-state??

    thanks

    Li

  • 0 in reply to Li Yang
    TI__Guru 69884 points

    Li

    This will depend on your FPGA JESD204B IP design. Most likely when the DAC is powered down, the FPGA will either send 0xBCBC (i.e. k28.5 handshaking code) or zero data encoded in 8b/10b. Therefore, you will have to incorporate design to ensure when DAC is powered down, the FPGA SerDes transmitter is tri-state.

  • 0 in reply to Kang Hsia
    TI__Guru 69884 points

    Li,

    The JESD204B requires the transmitter side to be stable in the JESD204 state machine before re-initializing the receiver state machine (i.e. DAC37J84). I would recommend you review the following documentation

    7.3.1.2.3 Link Initialization.docx

    with the focus on the following steps:

    Step 1 assumes that you have reset the FPGA JESD204 state machine, please follow step 2 to 3 to reset the DAC JESD204 receiver state machine to trigger a re-handshake to see if you system stability improves. 

    You do not need to keep resetting/repower the DAC in this case