• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 329 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AFE58JD48: When PLL_MODE = 80X, does AFE58JD48 JESD support 2-Lane mode?

AFE58JD28: About AFE58JD28 JESD 2 lane mode

APPLO ZHANG
Intellectual 515 points
Part Number: AFE58JD28

Does the following scenario support JESD 2 lane mode?

a.)MIXER enable, Decimation =3, Fs=40M

b.)MIXER enable, Decimation =6, Fs=80M

I have not seen any similar examples in the manual. If so, can you explain the settings?

Thanks!

  • +1
    TI__Expert 4701 points

    Hi,

    For case a, there Fs is 40MHz. For 2 lane, JESD need to run in 160x mode. So JESD speed will be 40*160x = 6.4Gbps. Which is supported. You have to configure the device in 8 ADCs per lane mode. Data format on  JESD, refere to figure "Figure 9-46. Illustration of Demod Output Data for JESD 8 ADC per LANE Mode with COMPR_FACTOR = 0, COMPR_FACTOR_JESD = 0" in the datasheet.

    For case b, Fs is 80MHz. You have to configure device in 4 ADCs per JESD lane mode and set compression factor to 1. So you will get data using 2 JESD lanes itself. Refer to "Figure 9-45. Illustration of Demod Output Data for JESD 4 ADC per LANE Mode with COMPR_FACTOR = 1, COMPR_FACTOR_JESD = 1" in datasheet for output format, Also refer to "Table 9-18. Channel Compression Logic for JESD Outputs" for knowing the active CML.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Intellectual 515 points

    Refer to "Table 9-18，as marked in the red box, DECIMATION FACTOR=6, 8ADC PER LANE MODE is also supported?
    Then, there is no 160X/80X/40X/20X mode similar to that described in AFED8JD48 in the AFE58JD28 data sheet. I don’t know if the internal hardware of the two chips is the same?

    If you combine the following two figures to see that the highest ADC sampling rate that 8ADC PER lane MODE can support is 40MHz



     However, the data rate below is less than the 6.4Gbps of the chip. Please help explain why it is not supported?
    8(AD)*2(I+Q)*16bit*80M*10/8/6 = 4.267Gbps

    Thanks!