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Original question:

AFE58JD28: About AFE58JD28 JESD 2 lane mode

AFE58JD28: About AFE58JD28 JESD 2 lane mode （2）

APPLO ZHANG
Intellectual 515 points
Part Number: AFE58JD28

Refer to "Table 9-18，as marked in the red box, DECIMATION FACTOR=6, 8ADC PER LANE MODE is also supported?
Then, there is no 160X/80X/40X/20X mode similar to that described in AFED8JD48 in the AFE58JD28 data sheet. I don’t know if the internal hardware of the two chips is the same?

If you combine the following two figures to see that the highest ADC sampling rate that 8ADC PER lane MODE can support is 40MHz



 However, the data rate below is less than the 6.4Gbps of the chip. Please help explain why it is not supported?
8(AD)*2(I+Q)*16bit*80M*10/8/6 = 4.267Gbps

Thanks!

  • 0
    TI__Expert 7565 points

    Hi,

    I understood the problem .  I will work out the details for M=6 and share it with you soon.

  • 0 in reply to Sachin H K
    TI__Expert 7565 points

    Hi,

    160x mode means - 8ADC per lane - ADC resolution is 16 bit and there is 8bit to 10 bit encoding in JESD - so 8(adc per lane)*16(resolution )*10/8 (jesd encoding) 

    Similarly 80x means (4 adc per lane ) , 40x means (2 Adc per lane ) 

    With decimation by 6 and mixer enable you can not got to 8adc per lane at FS = 80 MHz . In the 8adc per lane mode the max supported fs is 40MHz regardless of decimation .

    But you can put adc is 4 adc per lane mode and powerdown 2 cml lanes based on the compression setting used . So effectively 2 cml lane will be used in the system.

    The below table will show demod output format and jesd max supported speed