I decided to open another question since this is more to the operation of the EVM.
I am trying to characterize the operation of the ADC at different sampling rate, and thus I am trying to source an external clock to the EVM.
I am supplying a 1MHz 1.8Vpeak square wave into J6, and this is the measurement:
JP5 is modified to support EXT_CLK.
But I must be doing something wrong, as the result is completely wrong: Inputs at CH2 are connected to GND.
As comparison, this is the result with default FPGA clock:
