Original question:
Hello,
We are creating a FW project for our new ADC/DAC board that utilizes the ADS54J60 ADC and the DAC39J84 DAC. We are using the "TI204C-IP-Release-v1.12-LATEST" IP that in the README states that it works for 2022.x and above. However when synthesizing the IP core we run into problems with the following:
What exactly is happening on strings 13563, 13112, and 6 inside the encrypted sources?
We were able to resolve the issue in Vivado 2023.2
In the documentation it says that if only using the RX part of the IP functionality, that the unused attributes can be left as default. But that is what was causing the errors. We started again at the "zcu102_8b_10b" example and the synthesis was successful. We then tuned all of the unused parameters to meet our use case (i.e. all the TX related ones), that helped and the error inside of the encrypted IP disappeared.
Next we encountered an error about the I/O ports of the TI IP. Vivado requires that only VHDL or Verilog code be used on the top level of the project. The TI IP is written in System Verilog, so we created a wrapper in pure Verilog that just passes the signals along. However, the TI IP uses some specific types of signals (2d and 3d arrays) that pure Verilog cannot work with. So we created another wrapper in system Verilog that adapts all the specific I/O to the TI IP to the top level module.
Synthesis now passes
