ADS1293EVM: Negative cycle clipping in ADS1293 EVM

Hello Ajay,

Do you still need help with this issue?

What are the amplitude and common-mode voltages of your input sine wave? Can you provide the raw data for a few periods of samples using the ECG data and PACE data registers?

Regards,

Ryan

Hi Ryan,

Thank you for your response. We are providing a 500Hz sine wave signal via a 3.5mm audio jack and a +/- 200mV signal at the input. The attached zip file has an xlsx file with a plot of the graph that we created by converting the raw data as well as a raw data file for the ECG channel is also attached and Input Observed From CRO.

500hz.zip
However, when we use the same setup for the pace channel (+/- 200mV signal at input and 500Hz Sine wave signal from 3.5mm Audio Jack), we get negative cycle clipping when we try to obtain 10,000 samples per second. Is it possible to achieve a complete sine wave using the pace channel?

Thanks, Ajay. Even the data from the zip file looks a bit distorted when compared to the sine wave measured on the scope. This voltage is applied to IN2 and routed internally to INP, correct? What is the voltage applied to IN1 (used as INN)? For linear operation, the inputs to the instrumentation amplifier stage must follow the input common-mode voltage range below:

Can you check the status of the OUTP_HIGH/LOW and OUTN_HIGH/LOW error bits? 

Regards,

Ryan

Hi Ryan,

Every parameter has been examined. The data sheet is used to set it. We are able to read a complete sine wave at 800 Hz and 6400 sps after changing a few register configurations for a single channel. However, when we switch to the PACE channel, our negative signal is clipped. The register configurations for the ECG channel are shown below. Could you please advise us on what changes to make in order to obtain the correct output at 10,000 sps in the PACE channel?

void setup_ECG_data() {
writeRegister(0x00,0x00); //stop data conversion
writeRegister(0x01,0x0A); //Connect channel 1’s INP to IN1 and INN to IN2.
writeRegister(0x03,0x00);
writeRegister(0x04,0x00);
writeRegister(0x05,0x00);
writeRegister(0x06,0x00);
writeRegister(0x07,0x0F); //lead off detect enable for IN1,IN2,IN3 and IN4
writeRegister(0x08,0xFF); //setting lead off detect current
writeRegister(0x09,0x00); //clock driver factor k = 1(default)
writeRegister(0x0A,0x07); //common mode detect enable register
writeRegister(0x0B,0x00); //common mode detect control(default) (Low Bandwidth and Low cap drive mode)
writeRegister(0x0C,0x04); //RLD control Register
writeRegister(0x0D,0x00);
writeRegister(0x0E,0x00);
writeRegister(0x0F,0x00);
writeRegister(0x10,0x00);
writeRegister(0x11,0x00);
writeRegister(0x12,0x04); //clock source and output clock source
writeRegister(0x13,0x08); //AFE Increase sampling freq
writeRegister(0x14,0x00); //AFE shoutdown(All Active default)
writeRegister(0x15,0x00);
writeRegister(0x16,0x00);
writeRegister(0x17,0x05); //analog pace channel output routing control
writeRegister(0x18,0x00);
writeRegister(0x19,0x00);
writeRegister(0x1A,0x00);
writeRegister(0x1B,0x00);
writeRegister(0x1C,0x00);
writeRegister(0x1D,0x00);
writeRegister(0x21,0x01); //R2 decimation rate set to 4
writeRegister(0x22,0x01); //R3 decimation rate foe channnel 1 set to 4
writeRegister(0x23,0x02); //R3 decimation rate foe channnel 2 set to 4
writeRegister(0x24,0x02);
writeRegister(0x25,0x01); //Double pace data rate set to 2 for all channel(default)
writeRegister(0x26,0x00); //ECG filter enabled for channel 1,2 and 3 (default)
writeRegister(0x27,0x08); //driven by channel 1 ECG
writeRegister(0x28,0x00);
writeRegister(0x29,0x00); //optional masking for drdyd output(default)
writeRegister(0x2A,0x00);
writeRegister(0x2B,0x00);
writeRegister(0x2C,0x00);
writeRegister(0x2D,0x00);
writeRegister(0x2E,0x33);
writeRegister(0x2F,0x30);
writeRegister(0x30,0x00);
writeRegister(0x31,0x00);
writeRegister(0x32,0x00);
writeRegister(0x33,0x00);
writeRegister(0x34,0x00);
writeRegister(0x35,0x00);
writeRegister(0x36,0x00);
writeRegister(0x37,0x00);
writeRegister(0x38,0x00);
writeRegister(0x39,0x00);
writeRegister(0x3A,0x00);
writeRegister(0x3B,0x00);
writeRegister(0x3C,0x00);
writeRegister(0x3D,0x00);
writeRegister(0x3E,0x00);
writeRegister(0x3F,0x00);
writeRegister(0x40,0xFF);
writeRegister(0x50,0x00);
writeRegister(0x60,0x00);
writeRegister(0x62,0x00);
writeRegister(0x00,0x01); //start data convesion
}