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ADS54J60: Where to set M and S parameters in the JESD204C IP core for RX side

Part Number: ADS54J60

Hello,

We are trying to implement LMFS: 4-2-1-1 in the JESD IP core reference for the zcu102_8b_10b. We want to know which settings in "jesd_link_params.vh" need to be set for our the number of converters (M) and samples per converter per frame (S) for the RX parameters (we are just using XCVR RX lanes for our ADC).

We see in the "TI_204c_IP_ref.sv" that the parameters for M and S can be set for the TX parameters:

We would like to know if there is a similar setting for RX or if setting the TX in this way accomplishes the same task.

Thanks,

Ryan

  • Hi Ryan,

    These parameters aren't part of the Rx portion of the IP because the transport layer is not integrated in the TI JESD IP core. The mapping of lane data to samples is carried out in the refdesign_rx.sv file. These parameters were included with the Tx portion because they need to be included in the ILAS configuration (regardless of the whether the transport layer is integrated or not).

    In summary, for the Rx IP, the only important paramerters are the ones the bring up the link (thus presenting data on the lanes). The actual mapping is a manual edit in the refdesign_rx.sv file.

    Regards,

    Ameet

  • Thanks for the explanation Ameet.

    We have a couple questions regarding the JESDMODE register for LMFS=4211

    In one table we see the following:

    It says that the register should be set to 0x4 for LMFS=4211

    In the same document in a different table looks different:

    This table says that the register should be set to 0x2  (JESD MODE, 6-001h).

    Can you please share what the correct value for the JESDMODE register is for LMFS=4211?

  • Hi Ryan,

    Table 14 should be correct. For LMFS = 4211 you need to write 0x4. 0x2 is for LMFS = 4244.

    Thanks!

    Cheers,

    Fadi