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Original question:

ADS54J60: Where to set M and S parameters in the JESD204C IP core for RX side

ADS54J60: JESD204 IP Transceiver reference design

Ryan Carpenter
Prodigy 95 points
Part Number: ADS54J60

Hello,

There are the following parameters in the TI JESD IP's transceivers in the reference design 8b10b:
LaneRate = 12.5 Gbps
MGT_Ref_Clk = 156.25 MHz

We have MGT_Ref_Clk = LaneRate / 80, and it works, the QPLL inside the transceivers successfully locks.

However, we'd like to set MGT_Ref_Clk = LaneRate / 40 = 312.5 MHz;
We do it through the Vivado Transceivers Wizard and set the corresponding frequency value in the clock source.
But the QPLL stops locking after that. It works again only after returning the MGT_Ref_Clk back to 156.25 MHz.

Is it possible to change the MGT_Ref_Clk to other values?
If so, how can we do it correctly?

Thanks,

Ryan

  • 0
    TI__Intellectual 2260 points

    Hi Ryan,

    I am not sure why you are seeing the PLL lock issue. The MGT reference clock can be any value supported by the M/D parameters of the PLL, so if you are making the change in the transceiver wizard, it should work. Sometimes, the PLL lock seems tied to '0' because a change of lane rate forces the wizard to select QPLL1 (while the RTL still connects the lock of QPLL0 to the status VIO), but this isn't the case with your scenario.

    Kindly upload images of the first pane of the wizard, as it may help give an idea.

    Regards,

    Ameet

  • 0
    Prodigy 95 points

    Hello Ameet,

    We will look into this and provide you with the screenshot you requested.

    Thanks,
    Ryan