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ADS1278EVM-PDK: Data acquisition via SPI communication using Raspberry Pi

Part Number: ADS1278EVM-PDK

Tool/software:

Hi, I've recently been using an ADS1278v2EVM to capture data to my Raspberry Pi 4b, via SPI communication.
I saw someone else doing this, and there is a case that provides part of the wiring and code reference, I tried to follow his line of thought, but I have a problem that I can't solve: I don't know what causes, I can't read the data, I'll explain in detail my understanding of the problem below;
Very much hope you can give me some help.

After power on, the three power indicator lights are green and normal state.

Now the problem is: I can't collect the data;In the SPI protocol, DRDY goes high once SYNC goes low; DRDY stays high after SYNC returns high, and goes low once it is done retrieving valid data; after troubleshooting and testing, the code is stuck at “DRDY doesn't output a falling edge”.

The wiring between my ADS1278V2EVM and the Raspberry Pi is shown below:

J6 (The middle two columns correspond to the J6 pins of the ADS1278V2EVM, and the left and right columns correspond to the pins of the Raspberry Pi)    

22:GPIO6 FSDY SCLK SCLK
32:GPIO26 CLK DO1 MISO
0 DO2 DO3 0
0 DO4 DO5 0
0 DO6 DO7 0
0 DO8 DIN MOSI GND
16:GPIO1 SYNC EEWP 不接(原因未知)
GND GND GND GND

J4 (High Speed, SPI, TDM, Fixed Mode, Clock Input Divided to High Speed selected here)

M0 M1 F0 F1 F2 CLKDIV
0:open 0:open 1:short 0:open 0:open 1:short

JP1、JP2:(all 3-2 connection jumpers)

JP1——3 JP2——3
JP1——2 JP2——2
OPEN——1 OPEN——1

My code is:

import RPi.GPIO as GPIO
import spidev

# SPI setting
spi = spidev.SpiDev()
spi.open(0,0)  # spi.open(bus,device),连接到指定设备
spi.max_speed_hz = 7800000  # SCLK frequency 根据树莓派SPI速度列表
spi.mode = 0b00  # C_POL=0, C_PHA=0;SCLK空闲时为低电平,第一个时间沿采样;
spi.no_cs = True  # 设置SPI_NO_CS标志是否使用CS,此处使用CS

# get bytes
def adc_1ch():  # 1channel
    data = spi.xfer([0x00,0x00,0x00])  # 24bits = 3bytes,读取
    adc = (data[0] << 16) + (data[1] << 8) + data[2]  # shift register,将data24字节的数据转化为数值
    if adc > (2**23-1):  # 2's complement
        adc = adc - 2**24
    voltage = (adc*2.5)/(2**23 - 1)  # 此处参考电压是V(REF) = 2.5V,
    return voltage

def adc_8ch():  # 8channel
    ch = []
    for i in range(8):
        ch.append(adc_1ch())
    return ch


# GPIO setting,将SYNC和CLK都设为1,高电平
# 该函数将GPIO引脚22设置为输入模式,并将其状态设置为高电平。
GPIO.setmode(GPIO.BOARD)
pins = [16, 32]   # 物理接口
# SYNC, CLK Select pin
volt = [1,1]  # 1=high, 0=low
for p in range(2):
    GPIO.setup(pins[p],GPIO.OUT)
    if volt[p] == 1:
        GPIO.output(pins[p],GPIO.HIGH)
    else:
        GPIO.output(pins[p],GPIO.LOW)
# (新款PCB板可以通过跳线设置高低电平,所以此处只有SYNC和CLK需要编程实现高低电平)
GPIO.setup(22,GPIO.IN)  # DRDY pin 该函数将GPIO引脚22设置为输入模式,并将其状态设置为高电平。


# main
i = 0  # timer
while True:  # loop 100 times
    GPIO.wait_for_edge(22, GPIO.FALLING)  # start to capture data when DRDY falling down
    print(adc_8ch())  # capture data
    i = i + 1
    if i == 100:  # timer stop
        break
GPIO.cleanup()

  • Hello,

    The connections on J4 are inverted.  On the EVM, 1(high) is open, 0(low) is short.

    Below are the correct settings:

    J4 (High Speed, SPI, TDM, Fixed Mode, Clock Input Divided to High Speed selected here)

    M0              M1              F0              F1                F2                 CLKDIV
    0:short     0:short     1:open     0:closed     0:closed     1:open

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Many thanks! I've solved the problem and successfully collected data, I've compiled a list of the most difficult problems I encountered, and hopefully this will help anyone who needs it in the future;终极版_硬件接线+软件编程测试经过.pdf

    Problems encountered:

    1. The phenomenon of *not outputting results* or *long loading time* after running the code (solved)

    Process 1: After DEBUG it was found that it was caused by DRDY not having a falling edge and not being pulled down properly;

    According to reference one and two, it is guessed that it is caused by **SCLK not outputting the waveform needed by DRDY**;

    Reference I: correct timing waveform content (synchronized SYNC)

    Synchronization can be achieved by pulling the SYNC pin low and then returning the pin high; when the pin is low, the conversion stops; when the SYNC pin returns high, the conversion process restarts;

    In the SPI protocol, once SYNC goes low, DRDY goes high; after SYNC returns high, **DRDY stays high, and once the retrieval of valid data is done, DRDY goes low**;

    Reference 2: Proper Timing Waveform Content (SPI Serial Interface)

    The SPI compatibility mode is a read-only interface. Data ready to be read is indicated by the falling edge output of DRDY and is shifted out on the falling edge of SCLK with the MSB in front;

    **If no data is retrieved (i.e., SCLK remains low)**, DRDY pulses high just before the next conversion data is ready;

    Process 2: Using an oscilloscope to observe the SCLK waveform, it is found to be sinusoidal-like; CLK is similarly sinusoidal-like; and a normal clock signal should be a rectangular wave;

    Use the oscilloscope probe to note the ground line;? Not grounded is a rectangular wave?

    Reference 1: Reduce the communication rate;

    **Set f_sclk to 7629 or 15200 found that you can start outputting results and can increase the sclk frequency again**; !!!!!

    Reference 2: Check grounding;

    Be sure to check wiring several times;

    Reference 3: Shorten the signal wires;

    Indeed the extra signal line has a noise effect on the signal; because the oscilloscope to observe the signal, so the transfer to the breadboard went through a lot of transfer wires; after removing and rechecking: the CLK waveform is much closer to a rectangular waveform, and the SCLK has also improved;

    Doubt one: SCLK waveform

    Is the SCLK waveform fluctuating up and down at 0V similar to sine and rectangular waveforms?

    2. The real number of each channel is strange (solved)

    Phenomenon: 1-4 channels after the acquisition of the signal shows about 1.65V; 5-8 channel signal is about 0V;

    Suspected that the data shift problem, but after testing found to be a normal phenomenon:

    1-4 channel AIP1 and GND voltage is 1.65V;

    5-8 channel AIP1 and GND voltage is 0V;

    In the 5-channel 1 7 battery 1.65V, its output is 1.65V;

    When shorting channels 1-4, their outputs are all 0V;