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ADC3541: Need clarification for Output Data Format in Complex Decimation

Joseph Kleinman
Prodigy 20 points
Part Number: ADC3541
Other Parts Discussed in Thread: ADC3543

Tool/software:

We are currently experimenting with an ADC3543 on a custom board. We like to use the chip in complex decimation mode with parallel DDR output.

Figure 8-36 of the datasheet gives an example of the output format. According to the figure, D16 (MSB) down to D1 (LSB) are used with 16 bit output. I-samples seem to be present on the rising edge of DCLK, Q-samples on the falling edge.

This example does not really go well together with section 8.3.5.5 (Output Bit Mapper) of the datasheet, as Figure 8-44 (for parallel DDR mode) does not even provide addresses for anything below PIN D9. I see no possibility to configure the output bit mapping for PIN D1, D2, ..., D8. Also, I do not see how the addresses for rising and falling edges match to I and Q samples.

So from what I know now, I see two possible interpretations of the datasheet:

1. It is not possible to re-map bits at all in complex decimation output mode and the outputs are always fixed to D16 ... D1

2. The "parallel SDR" output mapping is used to map bits in complex decimation mode

Could you please elaborate a bit on the output bit mapping in complex decimation mode?

- Is interpretation 1) or 2) correct or maybe neither one?

- Is it possible to use more than 16 bits in complex decimation mode with parallel DDR output mode?

- Are there any additional configuration examples (with register contents) that you could provide for complex demication mode in DDR output mode?

Best regards!

  • 0
    TI__Intellectual 2280 points

    Hi Joseph,

    Sorry for the delay.

    The datasheet isn't as clear as it could be here, so apologies for that. I will give you now what appears to be correct, and in parallel will try to confirm with the design team on this.

    Interpretation 2 should be correct in this case. Figure 8-36 serves to show that when using complex decimation with DDR CMOS, the output configuration changes from what is shown in Figure 7-2. Figure 8-36 also shows that this format is the same as that shown for SDR mode.

    To address your point on addresses for rising and falling edge for I and Q samples, the following quote can be found at the top of page 50 of the datasheet: "When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample." So, you don't have to map rising and falling edge for this specific case.

    In parallel interface mode, the maximum output resolution is 18 bits. This is from page 48 of the datasheet.

    Again, I am working to confirm this with the design team but wanted to provide some feedback in the meantime.

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Prodigy 20 points

    Hi Drew,

    thank you for your reply. I did a lot experimenting during the last couple of days, but I just cannot get complex decimation with parallel DDR output to work as expected (i.e. as shown in the datasheet).

    If you could provide an example (sequence of register writes) to activate parallel DDR output with complex decimation, this would be extremely helpful!

    I tried multiple ways to initialize complex decimation with parallel DDR output, but I never got the outputs as expected (like in Figure 8-36, as verified by probing the output pins with an oscilloscope).

    As a result, we have currently disabled decimation and are implementing the digital downconversion (DDC) in our FPGA. However, this is an obvious waste of resources, as the ADC should be able to do this on-chip (and this is one of the reasons we selected this ADC in particular).

    Switching to complex decimation with serial output is probably also not an option, as this would imply very high (probably too high) data rates at the serial pins for our application.

    Best regards.

  • 0 in reply to Joseph Kleinman
    TI__Intellectual 2280 points

    Hi Joseph,

    Apologies for the delay. We are still working to clarify this with the design team.

    I will check back in with you Tuesday next week at the latest.

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    TI__Intellectual 2280 points

    Hi Joseph,

    A day late and we are still working on clarifying this. We are working to debug this.

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    TI__Mastermind 25040 points

    Hi Joseph,

    I am following up with design as Drew is OOO.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 20 points

    Hi Drew, Hi Rob.

    Thank you very much for working on this. We are eagerly waiting for updates on this. If there is anything we can already test or check, please let me know.

    Best regards